1. Acceptance of Terms
By visiting, viewing, or interacting with VLSIDesignFlow, you acknowledge that you have read, understood, and agreed to be bound by these Terms and Conditions and our Privacy Policy. If you do not agree to these terms, you must discontinue use of the portal immediately.
2. Educational & Reference Purpose
All materials, physical design flows, timing calculators, SDC timing constraints, Tcl scripts, and architectural guides on VLSIDesignFlow are provided strictly for educational, research, and technical reference purposes.
3. Intellectual Property & Trademarks
All commercial product names, logos, brands, and registered trademarks referenced on this portal (including Synopsys, Cadence Design Systems, Siemens EDA, Mentor Graphics, Ansys, Keysight Technologies, ARM, TSMC, Intel, and Samsung Foundry) are the property of their respective trademark holders. Reference to these commercial tools does not imply endorsement, affiliation, or sponsorship.
Open-source software referenced (including OpenROAD, OpenLane, Yosys, OpenSTA, KLayout, Magic, Netgen, Verilator, and SkyWater Sky130 PDK) are licensed under their respective open-source licenses (such as BSD-3-Clause, Apache 2.0, and GPL).
4. Permitted Use & Code Sandbox
You agree to use VLSIDesignFlow only for lawful purposes. You may freely study, copy, and modify open-source script snippets for your own academic or commercial design flows. You agree not to:
- Deploy automated bots or scraping tools to disrupt portal availability.
- Attempt to bypass security controls, inject malicious scripts, or perform denial-of-service (DDoS) attacks.
- Misrepresent affiliation with VLSIDesignFlow or its maintainers.
5. Disclaimer of Warranties & Silicon Tapeout Liability
THE PORTAL, SCRIPTS, SIMULATORS, AND CONTENT ARE PROVIDED "AS IS" AND "AS AVAILABLE" WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED. VLSIDESIGNFLOW DOES NOT GUARANTEE THAT CALCULATIONS, SCRIPTS, OR FLOWS WILL GUARANTEE ERROR-FREE FABRICATION OR SILICON YIELD ON ANY FOUNDRY PROCESS. USERS ASSUME FULL RESPONSIBILITY FOR SILICON TAPEOUT VALIDATION THROUGH OFFICIAL FOUNDRY-CERTIFIED SIGNOFF TOOLS (E.G., CALIBRE DRC/LVS, PRIMETIME STA).
6. Limitation of Liability
In no event shall VLSIDesignFlow, its authors, contributors, or maintainers be liable for any direct, indirect, incidental, special, consequential, or punitive damages (including loss of silicon wafers, mask fabrication costs, business interruption, or data loss) arising out of your use or inability to use this portal.
7. Contact & Questions
For inquiries regarding these Terms and Conditions, licensing queries, or technical feedback, please contact us via our Contact Page.