STA-MINMin Delay Signoff

Hold Slack & Minimum Delay Closure

The critical guide to Hold Time verification and race condition prevention in digital ICs. Unlike Setup violations which can be circumvented by reducing clock frequency, Hold violations are fatal silicon bugs ("Chip Killers") that completely brick fabricated chips. Hold analysis guarantees that new data does not race through fast logic paths and corrupt currently sampled data.

🛡️WHR ≥ 0.00 ns, THR = 0.00 nsSignoff Criterion

🏃Fast-Fast (FF) CornerWorst-Case PVT

❄️High VDD (1.10 × V_nom), -40°CThermal/Voltage

🚫Frequency-IndependentSilicon Behavior

SECTION 01 — SILICON PHYSICS & RACE CONDITIONS

Why Hold Violations are Fatal in Fabricated Silicon

💀 The "Chip Killer": Physical Mechanism of Hold Failure

During the active clock edge, the capturing flip-flop's internal master transmission gate (TG1) begins turning OFF. However, transmission gates are not instantaneous switches — they require a finite turn-off time (~30-150 ps) driven by the internal clock inverter (CLK_BAR).

If the data launched by the previous flip-flop travels across a short combinational path and reaches the capture flip-flop before TG1 is completely turned off and opaque, the new data penetrates into the master storage node and destroys the previous data before it can be transferred to the slave latch.

⚠️ The Fundamental Law of Hold Timing (Frequency Independence):

Setup checks compare launch at Cycle 0 with capture at Cycle 1 (T_period later). In contrast, Hold checks verify that launch at Cycle 0 does NOT overwrite capture at Cycle 0 (the SAME clock edge).

T_period DOES NOT EXIST in the Hold Equation!

Lowering the clock frequency from 1GHz to 100MHz (or even 1Hz) changes nothing. If a hold violation exists, the chip will fail at every conceivable operating frequency.

🔬 Transistor-Level Definition of Hold Time (T_hold)

Hold time (T_hold) is the minimum time the data input must remain stable after the active clock edge. Mathematically, it is dictated by the internal clock delay to the transmission gate minus the input stage propagation delay:

T_hold = t_clk_inverter + t_tg1_turn_off - t_input_buffer

In modern standard cell libraries, standard flip-flops are designed with internal delays to make T_hold near zero or slightly negative, but clock skew and fast interconnects can still create massive hold violations.

🔥 Short-Path Race Condition Anatomy

Shortest Paths: Direct register-to-register connections, scan chains, shift registers, and low-logic multiplexers.
Fastest Corner: Fast-Fast process, 1.95V, -40°C makes gate delays 2.5× faster than nominal.

SECTION 02 — MIN DELAY PATH TOPOLOGY & WAVEFORMS

Interactive Hold Timing Path & Race Condition Sandbox

Adjust fast-path delays, clock skew, hold constraints, or insert ECO delay buffers below. The aligned same-edge waveforms, hold sampling window (T_hold), and Hold Slack margin will dynamically update in real time.

MIN DELAY TOPOLOGY

Fast Data Race vs. Clock Skew at Fast-Fast Corner

🛡️

LIVE HOLD SLACK MARGIN

+0.25 ns (SAFE)

Min Arrival (T_arr,min):0.33 ns

Min Required (T_req,min):0.40 ns

Clock Skew:+0.20 ns

ECO Buffer Delay:+0.00 ns

🎉 Hold Timing Met: Data arrives at 0.33 ns, safely after the required hold stability window (0.40 ns). No race condition hazard in silicon.

⏱️ Dynamic Aligned Hold Waveforms (Same Active Clock Edge Analysis)

Interactive Real-Time SVG

SECTION 03 — MATHEMATICAL FORMULATION

Exact Mathematical Formulations for Hold Slack

FUNDAMENTAL MIN DELAY MODEL

1. Classical Hold Timing Formulations

Hold timing is evaluated on the same active clock edge (launch and capture initiated simultaneously at t = 0):

Data Arrival Time (T_arrival, min)

T_arrival,min = T_launch_clk,min + T_cq,min + T_comb,min

Calculated with minimum cell delays and min parasitic capacitances (best-case fast path).

Data Required Time (T_required, min)

T_required,min = T_capture_clk,max + T_hold + T_uncertainty_hold

Notice: T_period is absent! The requirement is strictly edge-referenced.

Hold Slack Formulation
Slack_hold = T_arrival,min - T_required,min ≥ 0.00 ns
Arrival must EXCEED Required. If Arrival < Required, Slack is negative (< 0.00 ns) = fatal failure.

VARIATION & CLOCK SKEW DYNAMICS

2. Clock Skew & CPPR Pessimism Removal

Clock skew acts in the exact opposite direction for Hold timing compared to Setup timing:

Clock Skew Impact on Hold Timing

T_skew = T_capture_clk - T_launch_clk

Positive Skew (T_skew > 0): Capture clock is delayed. HARMS Hold timing because the capture register continues waiting for old data while new data is already racing down the pipe!
Negative Skew (T_skew < 0): Capture clock arrives early. HELPS Hold timing.

Hold Formulation with CPPR / CRPR

Slack_hold = (T_lnch,min + T_cq,min + T_comb,min) - (T_capt,max + T_hold + T_unc - CPPR)

CPPR removes artificial delay divergence on shared clock tree buffers between launch and capture paths.

Required Buffer Delay for Hold ECO

ΔT_buf_delay ≥ |Slack_hold,neg| + Safety Margin (~0.10 ns)

SECTION 04 — SIGN-OFF ARTIFACTS

Annotated Real-World OpenSTA Hold Timing Report

Here is a real report generated by OpenSTA for a fast-path register endpoint on the SkyWater 130nm PDK at the Fast-Fast corner (-40°C, 1.95V):

timing_hold_ff_n40C_1v95.rptOpenSTA v2.5 / Sky130 HD

================================================================================
Path 1: MET Hold Check
Endpoint:   _09811_ (sky130_fd_sc_hd__dfxtp_1 clocked by clk)
Path Group: clk
Path Type:  min (Hold Check)
Corner:     fast (FF_n40C_1v95)
================================================================================

  Fanout     Cap    Slew    Delay     Time   Description
--------------------------------------------------------------------------------
                     0.00    0.00     0.00   clock clk (rise edge)
                             0.00     0.00   clock network delay (propagated)
       1    0.01     0.08    0.12     0.12 ^ clk_buf_0/X (sky130_fd_sc_hd__clkbuf_16)
       1    0.01     0.06    0.09     0.21 ^ _07421_/CLK (sky130_fd_sc_hd__dfxtp_1)
                             0.14     0.35 v _07421_/Q (sky130_fd_sc_hd__dfxtp_1)  <-- Fast T_cq (min)
       1    0.01     0.09    0.11     0.46 ^ hold_buf_1/X (sky130_fd_sc_hd__dly4_1) <-- Inserted ECO Buffer
       1    0.01     0.09    0.11     0.57 ^ hold_buf_2/X (sky130_fd_sc_hd__dly4_1) <-- Inserted ECO Buffer
       1    0.01     0.07    0.08     0.65 v _09811_/D (sky130_fd_sc_hd__dfxtp_1)
--------------------------------------------------------------------------------
                                      0.65   data arrival time (min)

                             0.00     0.00   clock clk (rise edge same cycle)
                             0.00     0.00   clock network delay (propagated)
       1    0.02     0.11    0.22     0.22 ^ clk_buf_capt/X (sky130_fd_sc_hd__clkbuf_16)
                             0.10     0.32 ^ _09811_/CLK (sky130_fd_sc_hd__dfxtp_1)
                             0.05     0.37   clock uncertainty                      <-- Hold Uncertainty
                             0.04     0.41   cell hold time                         <-- T_hold Library
--------------------------------------------------------------------------------
                                      0.41   data required time (min)
--------------------------------------------------------------------------------
                                      0.65   data arrival time (min)
                                     -0.41   data required time (min)
--------------------------------------------------------------------------------
                                      +0.24   slack (MET)

SECTION 05 — SILICON ECO PLAYBOOK

How to Fix Hold Timing Violations

🛡️

1. Delay Buffer Insertion

Insert dedicated delay buffers (e.g. `sky130_fd_sc_hd__dly4_1` or `buf_2`) into short data paths. Adds delay directly to T_arrival without altering logic functionality.

insert_buffer -net short_net_42 sky130_fd_sc_hd__dly4_1

🐌

2. Gate Downsizing

Replace over-sized fast drivers with lower drive-strength cells (e.g. `nand2_4` → `nand2_1`). Increases cell resistance and slows down output transition slew.

size_cell -cell _07421_ sky130_fd_sc_hd__dfxtp_1

🌱

3. Multi-Vt Swapping (LVT → HVT)

Swap fast Low-Vt cells to High-Threshold Voltage (HVT) or Ultra-High-Vt (uHVT) cells. HVT cells are naturally ~30% slower and eliminate static leakage power entirely!

swap_vt -cells [get_cells -of $hold_path] -to HVT

🐍

4. Wire Serpentining / Detouring

Route the net in a zig-zag or serpentine pattern across lower metal layers (Metal 1-2). Maximizes wire parasitic resistance (R) and capacitance (C) to introduce natural RC delay.

set_net_routing_rule -nets [get_nets $short_net] -layer M1_M2

⚖️

5. Clock Tree Balancing (CTS)

Trim clock insertion delay on the capture flip-flop clock branch to eliminate positive clock skew. Ensure clock arrivals across all register clusters are within ±50 ps.

balance_clock_tree -clock clk -max_skew 0.05

🏓

6. Beware the "Ping-Pong" Effect!

Always verify setup slack at the Slow-Slow corner before fixing hold at Fast-Fast corner. Inserting too many hold buffers can accidentally cause a setup violation on the same path!

check_timing_safety -setup_margin 0.20 -hold_margin 0.05

COMPLEMENTARY TIMING CHECK

Explore Setup Slack & Maximum Delay Analysis

Review the mathematical foundations of Setup Slack, master latch transmission gates, clock period constraints at the Slow-Slow corner, and gate upsizing ECOs.

Explore Setup Slack Deep Dive Return to STA Overview