01Front-End

System Specification & Design Handover

The starting point of every chip. A customer describes what they want — in plain words, performance targets and power budgets. The design team translates this into a formal specification document and architecture that every downstream engineer will follow for the next 12–18 months.

⏱️1–4 weeksTypical Duration

👥Architect + CustomerKey People

📄Spec Doc → RTL PlanDeliverable

🔧No EDA Tools YetTool Phase

SECTION 01 — STAGE DESCRIPTION

What Happens in System Specification?

🧩 The Architect's Job

Before writing a single line of Verilog, the chip architect must answer: What does this chip need to do, at what speed, at what power, in which process technology?

The customer provides requirements in natural language — "I need a 32-bit processor that runs at 50 MHz, fits in a 32-pin package, and consumes under 10 mW in active mode." The architect converts this into a formal document that defines every module, every interface, every timing budget, and which foundry and process node to use.

This document — the System Specification — becomes the contract between the customer and the design team. Every design decision downstream references it.

🏗️

Analogy: Like an architect's blueprint before construction. The builder (RTL engineer) cannot start without knowing room sizes, load-bearing walls and electrical specs. Spec errors caught here cost hours to fix. The same errors caught in silicon cost millions and 6+ months.

📋 What the Customer Provides

Functional requirements (what the chip computes)
Performance targets (MHz, latency, throughput)
Power budget (mW active, µW sleep)
Package type (QFN-32, BGA-256…)
Operating conditions (temperature, voltage)
Target process node (e.g., "130nm or below")

📐 What the Architect Produces

Block diagram showing all modules
Interface definitions (bus widths, protocols)
Clock domain plan (how many clocks, which MHz)
Power domain map (which blocks can sleep)
PPA targets per block (Area µm², Power mW, Freq MHz)
PDK selection & technology file checklist

SECTION 02 — INPUT / OUTPUT FILES

Files Flow: Stage 01 Inputs & Outputs

📥 INPUTS

requirements.pdf

Customer requirements document — functional description, performance targets, power budget in plain English

From: Customer

technology_node.spec

Chosen process node (SKY130 / GF180 / TSMC 28nm), package type, pin count

From: Customer + Architect

⚙️ STAGE 01 PROCESS

① Architecture Definition

② Block Diagram

③ Clock Domain Plan

④ Power Domain Map

⑤ PPA Target Setting

⑥ Spec Review & Sign-off

↓

📤 OUTPUT FILES

system_spec.pdf

Full specification document — block diagram, module specs, interface tables, PPA targets

→ Used by: RTL Engineers

constraints.sdc

Synopsys Design Constraints — clock definitions, IO delays, timing exceptions

→ Used by: Synthesis, STA

power_intent.upf

Unified Power Format — power domain definitions, isolation rules, retention specs

→ Used by: RTL, Synthesis

📊 REPORTS / SIGNOFF

spec_review_signoff.pdf

Customer-approved spec signoff — mandatory before RTL coding begins

Signoff: Customer + Lead Architect

ppa_budget.xlsx

Per-block PPA targets: Area (µm²), Power (mW), Max Frequency (MHz)

Signoff: Project Manager

SECTION 03 — REAL PROJECT WALKTHROUGH

PicoRV32 on SKY130: From Spec to Design Handover

🔬 OPEN-SOURCE PROJECT

ProjectPicoRV32 — Minimal RISC-V RV32IMC Processor

Sourcegithub.com/YosysHQ/picorv32

PDKSkyWater SKY130 (sky130_fd_sc_hd) — 130nm open PDK

Target50 MHz, 300µm × 300µm die, < 5 mW active

STEP 1

Customer Requirement (in plain words)

"I need a small 32-bit RISC-V processor core that can run embedded firmware at 50 MHz. It must fit in a 300µm × 300µm area on SkyWater 130nm, consume under 5 mW during active execution, and support memory-mapped IO for GPIO and UART."

This is Stage 01 input — what the customer says verbally or in a requirements document.

STEP 2

Architect's Translation → System Spec

## PicoRV32 System Specification v1.0
## PDK: SkyWater SKY130 (sky130_fd_sc_hd)

### Architecture
Core       : PicoRV32 (RV32IMC)
ISA        : RISC-V 32-bit Integer + Multiply + Compressed
Pipeline   : Single-issue, in-order, 2-4 CPI
Memory     : 2KB SRAM (instruction + data, shared)
Peripherals: GPIO (8-bit), UART (115200 baud)

### Clock Domains
sys_clk    : 50 MHz  (core + memory + GPIO)
uart_clk   : 1.8432 MHz (derived from sys_clk via divider)

### Power Domains
pd_core    : CPU + SRAM (can be clock-gated)
pd_always_on: Reset logic, clock divider (never off)

### PPA Targets
Area       : ≤ 90,000 µm²   (300µm × 300µm die, 70% util)
Power      : ≤ 5 mW @ 50 MHz, 1.2V
Frequency  : 50 MHz at SS/100°C corner (worst case)

### PDK Technology Files (from SkyWater/Efabless)
sky130_fd_sc_hd__tt_025C_1v80.lib   ← Timing (TT corner)
sky130_fd_sc_hd__ss_100C_1v60.lib   ← Timing (SS corner)
sky130_fd_sc_hd.lef                 ← Cell geometry
sky130.tech                         ← Design rules
sky130_fd_pr__base.spice            ← SPICE models

STEP 3

SDC Timing Constraints File (constraints.sdc)

## picorv32_constraints.sdc
## Stage 01 output — defines timing targets for all downstream tools

# Primary clock: 50 MHz system clock
create_clock -name sys_clk -period 20.0 [get_ports clk]
#   → period = 1/50MHz = 20 ns

# Clock uncertainty (jitter + skew budget)
set_clock_uncertainty 0.5 [get_clocks sys_clk]
#   → 0.5 ns uncertainty = 2.5% of clock period

# Input delays (assume signals arrive 2 ns after clock edge)
set_input_delay  -clock sys_clk -max 2.0 [get_ports {resetn mem_ready mem_rdata}]

# Output delays (outputs must be stable 2 ns before next clock edge)
set_output_delay -clock sys_clk -max 2.0 [get_ports {mem_valid mem_addr mem_wdata}]

# Operating conditions
set_operating_conditions -library sky130_fd_sc_hd__ss_100C_1v60
#   → Use slow-slow corner at 100°C, 1.6V for worst-case timing check

SECTION 04 — EDA TOOLS

Tools Used in System Specification Stage

At Stage 01, heavy EDA tools are not yet needed. The work is mostly documentation and constraint writing. However, the PDK files you choose here dictate which tools you will use in all downstream stages.

Task	🏭 Synopsys	🔷 Cadence	🟧 Siemens EDA	🔓 Open-Source
Specification & Architecture Documentation	—	—	—	Markdown · Git Wiki · draw.io
Block Diagram & Micro-Architecture	Synopsys Platform Architect	Cadence System Studio	—	draw.io · Excalidraw · Mermaid
Timing Constraints Authoring (SDC)	Synopsys PrimeTime (SDC reference)	Cadence Tempus	—	OpenSTA · any text editor
Power Intent Authoring (UPF)	Synopsys SpyGlass	Cadence Joules / Genus	Questa Power Aware	Any text editor (UPF = plain text)
PDK Setup & Library Management	Synopsys SiliconSmart	Cadence Library Characterizer	—	skywater-pdk · volare · LibreCell