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LEGAL & DATA PRIVACY

Privacy Policy

Last Updated: August 2026. This policy outlines how VLSIDesignFlow collects, handles, and protects your information when using our educational semiconductor portals, interactive timing calculators, and EDA directory.

1. Overview & Open-Source Commitment

VLSIDesignFlow is dedicated to open-source semiconductor design and education. We believe in absolute transparency, user privacy, and data minimization. We do not sell, rent, monetize, or trade your personal data with third-party advertisers or data brokers under any circumstances.

2. Information We Collect

When you access or interact with VLSIDesignFlow:

  • Voluntary Contact Information: If you reach out to us via our contact form or official email, we collect your name, email address, and message content solely to respond to your inquiry.
  • Client-Side Local Storage: Interactive simulators (such as the Setup & Hold timing engines, Tcl script playground, and theme preference toggles) store your preferences locally in your browser (LocalStorage). This data never leaves your device.
  • Anonymous Server Logs & Telemetry: Standard web server logs may temporarily record anonymous technical metrics such as browser user-agent, IP address, and requested pages to ensure server uptime, prevent DDoS attacks, and optimize page load performance.

3. Cookies & Tracking Technologies

VLSIDesignFlow operates without invasive third-party cross-site trackers or behavioral advertising cookies. We only utilize essential first-party cookies and browser LocalStorage strictly necessary for portal functionality (e.g., remembering your dark/light theme choice and active simulator presets).

4. Third-Party Links & External Documentation

Our portal contains direct outbound hyperlinks to external documentation repositories (including OpenROAD ReadTheDocs, OpenLane GitHub, SkyWater PDK, Synopsys, Cadence, and Siemens EDA). When clicking these external links, you are directed to third-party domains governed by their respective privacy policies.

5. Data Security & Retention

We employ industry-standard HTTPS/TLS encryption across all endpoints. Anonymous server access logs are routinely pruned and rotated. Communications submitted via our contact channel are retained only for the duration necessary to resolve technical inquiries.

6. Your Data Rights

Depending on your jurisdiction (such as GDPR in the EU or CCPA in California), you have the right to request access to, correction of, or deletion of any personal communications held by us. To exercise these rights, please reach out via our Contact Page.

7. Policy Amendments

We may periodically update this Privacy Policy to reflect platform enhancements or legal requirements. Material modifications will be reflected with an updated timestamp at the top of this document.

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VLSIDesignFlow

Next-generation physical design platform empowering semiconductor engineers with open-source RTL-to-GDSII tools and automated tapeout workflows.

Front-End & Synthesis

  • 01. System Spec & Handover
  • 02. RTL Design & Verification
  • 02a. CDC & UPF Power Intent
  • 02b. BIST & JTAG Insertion
  • 03. Logic Synthesis
  • 03a. Formal Logic Equivalence (LEC)
  • 03b. Scan Chain & ATPG

Physical Design & Signoff

  • 04. Floorplan & PDN Grid
  • 05. Standard Cell Placement
  • 06. Clock Tree Synthesis (CTS)
  • 07. Global & Detailed Routing
  • 08. Parasitics (SPEF) & Power
  • 09. Physical Signoff (DRC/LVS)
  • STA Timing Analysis Deep-Dive
  • ↳ Setup Slack (Max Delay)
  • ↳ Hold Slack (Min Delay)

Resources & Support

  • EDA Tools Directory
  • Tcl Script Playground
  • Contact & Support
  • OpenROAD Docs ↗
  • OpenLane 2 Guide ↗
  • SkyWater Sky130 PDK ↗
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