CDC Analysis & UPF Power Intent
Modern SoCs integrate multiple asynchronous clock domains and complex power management states. This stage verifies that every signal crossing between independent clocks is protected against metastability using robust synchronizers, while formally defining power domains, voltage islands, level shifters, and isolation rules in Unified Power Format (UPF / IEEE 1801).
What Happens in CDC & UPF Power Intent?
🧩 The Low-Power & Asynchronous Architect's Job
Real-world microchips rarely operate on a single clock. A typical SoC runs a high-speed CPU clock (e.g. 50–500 MHz), a low-power real-time clock (RTC @ 32.768 kHz), and asynchronous peripheral clocks (UART, SPI, USB). When a signal generated in one clock domain is sampled by a flip-flop in another domain without a fixed phase relationship, the receiving flip-flop's setup or hold window will eventually be violated, causing metastability — where the output oscillates unpredictably before settling to a random 0 or 1.
The CDC architect identifies every cross-domain boundary and enforces proven synchronization topologies: 2-flip-flop synchronizers for single-bit control flags, Gray-coded dual-clock FIFOs for multi-bit data words, and request/acknowledge handshake protocols. Reset Domain Crossing (RDC) checks ensure asynchronous reset deassertion is glitch-free.
Concurrently, the power architect writes the UPF (IEEE 1801) specification. Rather than hardcoding power switches into RTL, UPF declaratively specifies voltage islands, power switches for sleep modes, isolation cells to clamp outputs of powered-off blocks to safe logic levels, level shifters for voltage domain boundaries (e.g. 1.8V IO to 1.2V Core), and retention registers to preserve critical state during sleep.
📋 What RTL & Spec Provide
- Multi-clock RTL description (clocks & resets)
- SDC master clock definitions & generated clocks
- Power architecture targets & voltage domains
- Sleep / Wakeup power state transitions
- Retention register candidate list
- Analog/Sensor IO voltage interface requirements
📐 What the CDC/UPF Team Produces
- Validated UPF 3.0 / IEEE 1801 power intent file
- CDC verification signoff report (0 unsynchronized nets)
- RDC verification signoff report (glitch-free resets)
- Verified 2-FF, MUX-recirculating & FIFO sync modules
- Isolation & level-shifter cell insertion rules
- Power State Table (PST) covering all operational modes
Files Flow: Stage 02a Inputs & Outputs
PicoRV32 on SKY130: CDC Synchronizers & UPF 3.0 Intent
Hardened 2-FF Synchronizer (sync_2ff.v)
// sync_2ff.v - 2-Stage Flip-Flop Synchronizer for Single-Bit CDC
(* dont_touch = "true" *)
module sync_2ff (
input wire clk_dest, // Destination clock domain (e.g., 50 MHz sys_clk)
input wire rst_n, // Destination active-low reset
input wire async_in, // Asynchronous input from source clock domain
output wire sync_out // Synchronized output in destination domain
);
(* ASYNC_REG = "TRUE" *) reg stage1_reg;
(* ASYNC_REG = "TRUE" *) reg stage2_reg;
always @(posedge clk_dest or negedge rst_n) begin
if (!rst_n) begin
stage1_reg <= 1'b0;
stage2_reg <= 1'b0;
end else begin
stage1_reg <= async_in; // First flop: captures input (may go metastable)
stage2_reg <= stage1_reg; // Second flop: samples resolved stable level
end
end
assign sync_out = stage2_reg;
endmoduleUPF 3.0 Power Specification (picorv32_power.upf)
## picorv32_power.upf - IEEE 1801 Power Intent Specification
upf_version 3.0
# 1. Create Power Domains
create_power_domain pd_top -include_scope
create_power_domain pd_aon -elements {u_pmu u_rtc}
create_power_domain pd_core -elements {u_picorv32_cpu u_sram_2kb}
# 2. Supply Ports and Nets
create_supply_port VDD_AON -direction in
create_supply_port VDD_CORE -direction in
create_supply_port VSS -direction in
create_supply_net VDD_AON -domain pd_aon
create_supply_net VDD_CORE -domain pd_core
create_supply_net VSS -domain pd_top -reuse
# 3. Isolation Strategy: Clamp core outputs to 0 when core is powered off
set_isolation core_iso \
-domain pd_core \
-isolation_power_net VDD_AON \
-isolation_ground_net VSS \
-clamp_value 0 \
-applies_to outputs
# 4. Level Shifter Strategy: Translate 1.8V IO to 1.2V Core
set_level_shifter io_to_core_ls \
-domain pd_core \
-applies_to inputs \
-rule both \
-location toCDC & UPF Lint Verification Report (cdc_summary.rpt)
=== CDC & UPF Structural Signoff Report: PicoRV32 ===
Design Top : picorv32_top
Clocks : sys_clk (50MHz), rtc_clk (32.768kHz), uart_clk (1.8432MHz)
--- CDC Domain Crossing Matrix ---
Total Signal Crossings Identified : 48
[PASS] Single-bit control signals : 32 (Synchronized via sync_2ff)
[PASS] Multi-bit data buses : 12 (Synchronized via Async FIFO + Gray code)
[PASS] Reset crossings : 4 (Deassertion synchronizers verified)
[FAIL] Unsynchronized violations : 0 ✓
--- UPF Power Intent Structural Verification ---
Power Domains Configured : 3 (pd_top, pd_aon, pd_core)
Isolation Strategies : 1 (142 output ports protected, clamp=0)
Level Shifter Strategies : 1 (32 IO-to-Core ports protected)
Retention Registers : 8 (CPU state preserved during DEEP_SLEEP)
Missing Isolation Cells : 0 ✓
Power State Table Status : CONSISTENT (ACTIVE, STANDBY, DEEP_SLEEP)
STATUS: STAGE 02a CDC & UPF SIGNOFF COMPLETE - PASSTools Used in CDC & UPF Stage
Cross-domain verification requires specialized structural analysis engines to identify asynchronous paths and power domain interfaces before synthesis.
| Task | 🏭 Synopsys | 🔷 Cadence | 🟧 Siemens EDA | 🔓 Open-Source |
|---|---|---|---|---|
| Clock Domain Crossing (CDC) Analysis | Synopsys SpyGlass CDC | Cadence Conformal CDC | Siemens Questa CDC | Verilator CDC Rules · SVA Assertions |
| Reset Domain Crossing (RDC) Verification | Synopsys SpyGlass RDC | Cadence JasperGold RDC | Siemens Questa RDC | Custom SVA Reset Assertions |
| UPF / Low-Power Static Rule Checking | Synopsys VC LP (Low Power) | Cadence Conformal Low Power | Siemens Questa Power Aware | PyUPF · Custom UPF Parsers |
| Power-Aware Dynamic RTL Simulation | Synopsys VCS NLP (Native LP) | Cadence Xcelium LP | Siemens QuestaSim PA | Icarus Verilog + VPI Power Mock |
| RTL Power Profiling & Activity Mapping | Synopsys PrimePower RTL | Cadence Joules RTL Power | Siemens PowerPro | pyVCD · RTL Power Estimators |