Global & Detailed Routing & Antenna/Metal Fill
Creating physical copper/aluminum interconnect wires across all standard cell and macro pins. Global routers (FastRoute) plan routing channels across global routing cells (G-cells), detailed routers (TritonRoute) assign exact metal tracks on interconnect layers (Met1–Met5) enforcing nanometer DRC rules, gate-protection diodes suppress plasma antenna charge damage, and dummy metal fill achieves Chemical-Mechanical Polishing (CMP) density compliance.
What Happens in Detailed Routing & Metal Fill?
🧩 The Routing Engineer's Job
Once standard cells and clock trees are placed, the detailed wiring phase connects millions of logical nets across multiple physical metal layers. Routing proceeds in two coordinated stages: Global Routing and Detailed Routing.
The global router (FastRoute) partitions the entire die into a 3D grid of Global Cells (G-cells). It determines which metal layers each net should traverse (short local connections on Met1–Met3, long buses and clocks on Met4–Met5) and outputs 3D geometric guides, ensuring no routing channel exceeds its maximum track capacity. The detailed router (TritonRoute) then follows these guides, placing exact polygon wires and inter-layer contact vias while rigorously enforcing hundreds of foundry Design Rule Check (DRC) constraints: minimum wire width, parallel run length spacing, end-of-line spacing, and via enclosure rules.
During semiconductor fabrication, plasma etching accumulates electrostatic charges on long metal wires — the Antenna Effect — which can discharge through thin MOSFET gate oxides and permanently destroy transistors. The routing flow analyzes antenna ratios and inserts Gate-Protection Diodes to safely shunt charge to ground. Finally, Dummy Metal Fill patterns are deposited across sparse regions of each metal layer to meet foundry metal density rules (typically 35–65%) required for uniform wafer planarization during Chemical-Mechanical Polishing (CMP).
📋 What CTS Provides
- CTS DEF with placed cells & clock buffer tree
- Technology LEF with layer spacing & via rules
- Layer pitch and preferred routing directions (H/V)
- Antenna ratio DRC design rules from foundry
- CMP metal layer density target windows (35–65%)
- Propagated SDC timing constraints
📐 What the Routing Engineer Produces
- Fully routed DEF file (all nets connected)
- Routed DEF with antenna diodes & dummy metal fill
- 0 DRC violation report (zero shorts and zero opens)
- Antenna rule check signoff report (0 gate oxide risks)
- Chemical-Mechanical Polishing (CMP) density report
- Post-route parasitics ready for SPEF signoff
Files Flow: Stage 07 Inputs & Outputs
PicoRV32 on SKY130: TritonRoute Detailed Routing
OpenROAD Global & Detailed Routing Script (routing.tcl)
# OpenROAD FastRoute Global Routing Execution
read_def picorv32_cts.def
read_sdc post_cts_constraints.sdc
# 1. Global Routing with Congestion-Driven Track Assignment
global_route \
-guide_file picorv32.guide \
-layers 1 5 \
-clock_layers 4 5 \
-overflow_iterations 50
# 2. Detailed Routing via TritonRoute
detailed_route \
-guide picorv32.guide \
-output_drc picorv32_drc.rpt \
-output_maze picorv32_maze.log \
-verbose 1Antenna Diode Insertion & Dummy Metal Fill Script
# 1. Check Antenna Ratio Violations on Routed Metal Lines
check_antennas -report_file antenna_violations.rpt
# 2. Automatically insert gate-protection diodes for violating nets
insert_antenna_diodes \
-diode_cell "sky130_fd_sc_hd__diode_2" \
-diode_pin "DIODE"
# 3. Insert Dummy Metal Fill Patterns for CMP Planarity
density_fill \
-layers {met1 met2 met3 met4 met5} \
-target_density 0.45
# 4. Export Finalized Routed DEF
write_def picorv32_routed_filled.defRouting & DRC Clean Signoff Report (routing_signoff.rpt)
=== TritonRoute Detailed Routing Signoff: PicoRV32 ===
Design Top : picorv32_top
Technology : SkyWater SKY130 (5 Metal Layers)
--- Routing Wirelength & Via Statistics ---
Layer met1 (li1) : 1.42 meters
Layer met2 : 2.18 meters
Layer met3 : 2.05 meters
Layer met4 : 0.88 meters (Clocks & Power)
Layer met5 : 0.32 meters (Clocks & Power)
Total Wire Length : 6.85 meters
Total Vias Placed : 48,200 vias
--- Design Rule Checking (DRC) Summary ---
Short Violations : 0
Open Violations : 0
Spacing Violations : 0
TOTAL DRC ERRORS : 0 (100% DRC CLEAN PASS)
--- Antenna & CMP Planarity Signoff ---
Antenna Ratio Max : 184.2 (Foundry Limit < 200.0 PASS)
Diodes Inserted : 42 instances
Average Metal Dens : 48.2% across all layers (35-65% PASS)
STATUS: STAGE 07 DETAILED ROUTING COMPLETE - PASSTools Used in Routing & Metal Fill Stage
Detailed routing engines must satisfy thousands of complex nanometer geometric design rules while preserving signal integrity and closing timing.
| Task | 🏭 Synopsys | 🔷 Cadence | 🟧 Siemens EDA | 🔓 Open-Source |
|---|---|---|---|---|
| Global Routing & Track Assignment | Synopsys IC Compiler II (Z-Route Global) | Cadence Innovus NanoRoute (Global) | Siemens Aprisa Global Router | OpenROAD (FastRoute) |
| Detailed Nanometer Routing & Via Gen | Synopsys ICC2 Detailed Router | Cadence Innovus NanoRoute (Detailed) | Siemens Aprisa Detailed Router | OpenROAD (TritonRoute) |
| Antenna Effect Checking & Diode Fix | Synopsys ICC2 Antenna Engine | Cadence Innovus Antenna Fixer | Siemens Aprisa Antenna Fixer | OpenROAD (insert_antenna_diodes) |
| Dummy Metal Fill Generation (CMP) | Synopsys IC Validator Metal Fill | Cadence Pegasus Metal Fill | Siemens Calibre YieldEnhancer | KLayout Metal Fill Scripts |
| Post-Route Physical Verification & STA | Synopsys PrimeTime (Post-Route) | Cadence Tempus (Post-Route) | Siemens Questa Timing | OpenSTA (post-route) |