Tcl & Python Script Simulator
EDA Automation Script Playground
Write, execute, and experiment with production-ready Tcl & Python automation scripts for OpenROAD, Yosys, and OpenLane 2 flows in an interactive terminal simulator.
SCRIPT LAB
OpenROAD & OpenLane Script Playground
Inspect production-grade Tcl automation scripts and JSON configuration schemas used to drive physical synthesis, floorplanning, CTS, and detailed routing.
1
{
2
"DESIGN_NAME": "riscv_core_top",
3
"VERILOG_FILES": ["dir::src/riscv_core_top.v", "dir::src/alu.v", "dir::src/regfile.v"],
4
"CLOCK_PORT": "clk",
5
"CLOCK_PERIOD": 10.0,
6
"PDK": "sky130A",
7
"STD_CELL_LIBRARY": "sky130_fd_sc_hd",
8
"FP_CORE_UTIL": 65,
9
"FP_PDN_CORE_RING": true,
10
"PL_TARGET_DENSITY": 0.68,
11
"CTS_CLK_BUFFERS": ["sky130_fd_sc_hd__clkbuf_4", "sky130_fd_sc_hd__clkbuf_8"],
12
"GRT_ALLOW_CONGESTION": false,
13
"DRT_OPT_MODE": 2
14
}
1
# OpenROAD Floorplan & Power Distribution Network (PDN)
2
read_lef $PDK_ROOT/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef
3
read_def ./results/synthesis/synthesis.def
4
5
# Initialize die core area boundary (1.2mm x 1.2mm)
6
initialize_floorplan -die_area "0 0 1200 1200" \
7
-core_area "100 100 1100 1100" \
8
-site unithd
9
10
# Place SRAM memory macro blocks with placement halos
11
place_macro -inst_name "u_sram_32k_0" -location "150 750" -orientation R0
12
place_macro -inst_name "u_sram_32k_1" -location "650 750" -orientation MY
13
add_macro_halo -inst_name "u_sram_32k_0" -halo "10 10 10 10"
14
15
# Generate VDD/VSS Power Distribution Mesh (Met4/Met5)
16
define_pdn_grid -name "core_grid" -starts_with "POWER"
17
add_pdn_stripe -grid "core_grid" -layer "met4" -width 1.6 -pitch 27.2 -offset 13.6
18
add_pdn_stripe -grid "core_grid" -layer "met5" -width 1.6 -pitch 27.2 -offset 13.6
19
gen_pdn
1
# Clock Tree Synthesis & Buffer Insertion (TritonCTS)
2
read_sdc ./constraint/clock_sdc.sdc
3
4
# Configure TritonCTS Clock Buffer Roots
5
set_clock_tree_max_fanout 16
6
set_clock_tree_max_slew 0.2
7
set_clock_tree_buffers "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8 sky130_fd_sc_hd__clkbuf_16"
8
9
# Run CTS Buffer Tree Synthesis
10
clock_tree_synthesis -root_buf sky130_fd_sc_hd__clkbuf_16 \
11
-buf_list "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8" \
12
-wire_unit 20
13
14
# Repair Clock Hold Violations
15
repair_clock_inverters
16
repair_timing -hold
1
# Global & Detailed Routing with TritonRoute
2
global_route -guide_file ./results/route.guide \
3
-congestion_iterations 50 \
4
-verbose 1
5
6
# Detailed Routing Execution
7
detailed_route -param_file ./results/tritonRoute.param \
8
-guide_file ./results/route.guide \
9
-output_def ./results/route/routed.def \
10
-output_drc ./results/route/drc.rpt
11
12
# SPEF Parasitics Extraction for STA Signoff
13
write_spef ./results/route/spef_parasitics.spef