STATiming Engine

Static Timing Analysis & Timing Closure

The mathematical verification backbone of digital semiconductor design. Static Timing Analysis (STA) executes across Synthesis (03), Placement (05), CTS (06), and Post-Route (07/08) to exhaustively calculate Setup and Hold Slack across all Multi-Corner Multi-Mode (MCMM) PVT libraries without test vectors, mathematically guaranteeing zero timing violations in fabricated silicon.

⏱️Multi-StageTypical Duration

👥Timing Signoff EngineerKey People

📄Timing Closure (WNS ≥ 0, WHR ≥ 0)Deliverable

🔧OpenSTA, PrimeTime, TempusTool Phase

SECTION 01 — STAGE DESCRIPTION

What Happens in Static Timing Analysis (STA)?

🧩 The Timing Signoff Engineer's Job

Traditional dynamic gate-level simulation would require billions of test vectors and weeks of compute time, and still might miss the single worst-case data path. Static Timing Analysis solves this by mathematically decomposing every digital circuit into four timing path types: Register-to-Register, Input-to-Register, Register-to-Output, and Input-to-Output.

The timing engineer calculates propagation delays through every logic gate using Non-Linear Delay Models (NLDM) or Composite Current Source (CCS) tables from the foundry's Liberty (.lib) library, factoring in input transition slew and output capacitive load (C_load).

The ultimate goal is Timing Closure: ensuring that every single sequential register satisfies both Setup and Hold timing requirements across all operating PVT corners and voltage modes with Worst Negative Slack (WNS ≥ 0.00 ns) and Total Negative Slack (TNS = 0.00 ns).

🏗️

Analogy: Like calculating the legal handoff window in an Olympic 4x100m relay race. The baton receiver cannot run so fast that they exit the 20-meter changeover zone before the incoming runner arrives (Hold violation / data race), nor can the incoming runner take too long and arrive after the receiver crosses the line (Setup violation). Both runners must time their strides to arrive inside the legal window.

📋 What Design Stages Provide

Gate netlists at Synthesis, Placement, CTS & Route
Characterized Liberty (.lib) PVT libraries
Synopsys Design Constraints (.sdc)
Multi-corner extracted SPEF parasitics
False path & multicycle timing exceptions
Clock uncertainty & jitter budgets

📐 What the STA Specialist Produces

Setup slack report at Slow-Slow corner (WNS ≥ 0)
Hold slack report at Fast-Fast corner (WHR ≥ 0)
WNS / TNS summary matrix across all PVT corners
Max transition (slew) & max capacitance report
Clock skew and insertion delay summary
Automated ECO timing fix script for tapeout

CORE TIMING CONCEPTS

Setup Time vs. Hold Time: Mathematical Formulations & Silicon Physics

Digital sequential circuits sample data on the active clock edge. For a flip-flop to reliably capture data without entering a metastable state, data must satisfy two fundamental timing windows:

⏱️

1. Setup Time Check (Max Delay)

Evaluated at Slow-Slow (SS) Corner

Setup Time (T_setup) is the minimum time the data input must remain stable before the arrival of the active clock edge at the capturing flip-flop.

DATA ARRIVAL TIME (MAX)

T_arrival = T_{launch_clk} + T_cq + T_{comb_max}

DATA REQUIRED TIME (MAX)

T_required = T_period + T_{capture_clk} - T_setup - T_uncertainty

SETUP SLACK (MUST BE ≥ 0)

Slack_setup = T_required - T_arrival ≥ 0.00 ns

Silicon Operating Conditions: Worst-case low voltage (1.60V), high temperature (+100°C to +125°C), slow transistor process corner (SS), and max RC parasitic interconnect delays.
How to Fix Setup Violations:

Upsize logic gates (e.g. swap `nand2_1` → `nand2_4` for higher drive strength)
Swap high-threshold (HVT) cells to low-threshold (LVT) for faster switching
Reduce combinational logic levels between registers
Leverage useful clock skew (delay clock to capture flip-flop)

Explore Setup Slack Deep-Dive & Waveforms

🛡️

2. Hold Time Check (Min Delay)

Evaluated at Fast-Fast (FF) Corner

Hold Time (T_hold) is the minimum time the data input must remain stable after the arrival of the active clock edge to prevent newly launched data from corrupting the current capture.

DATA ARRIVAL TIME (MIN)

T_arrival = T_{launch_clk} + T_cq + T_{comb_min}

DATA REQUIRED TIME (MIN)

T_required = T_{capture_clk} + T_hold + T_uncertainty

HOLD SLACK (MUST BE ≥ 0)

Slack_hold = T_arrival - T_required ≥ 0.00 ns

Silicon Operating Conditions: Best-case high voltage (1.95V), sub-zero temperature (-40°C), fast transistor process corner (FF), and min RC parasitic interconnect delays.
Key Insight & How to Fix Hold Violations:

Frequency Independent: Hold slack does NOT depend on clock period (T_period) — slowing down the clock will NOT fix hold violations!
Hold violations MUST be fixed in physical silicon by inserting delay buffers on short data paths
Increase wire length / route detours on fast combinational paths

Explore Hold Slack Deep-Dive & Physics

Setup vs. Hold Timing Comparison Summary

Characteristic	Setup Timing (Max Delay)	Hold Timing (Min Delay)
Definition	Data must arrive ≥ T_setup before clock edge	Data must stay stable ≥ T_hold after clock edge
PVT Signoff Corner	Slow-Slow (SS) / Low VDD / High Temp (+100°C)	Fast-Fast (FF) / High VDD / Low Temp (-40°C)
Clock Period Dependency	Dependent on T_period (can fix by lowering clock freq)	Independent of T_period (frequency-independent)
Physical Fix	Upsize cells, swap HVT → LVT, logic reduction	Insert delay buffer cells (`buf_1`, `buf_2`) on data path
Signoff Gate	Worst Negative Slack (WNS) ≥ 0.00 ns	Worst Hold Slack (WHR) ≥ 0.00 ns
Dedicated Guide	👉 View Setup Slack Deep-Dive →	👉 View Hold Slack Deep-Dive →

SECTION 02 — INPUT / OUTPUT FILES

Files Flow: STA Inputs & Outputs

📥 INPUTS

picorv32_routed.v / .def

Gate-level netlist and physical layout from Synthesis, Placement, CTS, or Routing

From: Stages 03, 05, 06, 07

sky130_pvt_corners.lib

Multi-corner Liberty models: SS_100C_1v60.lib (Slow), TT_025C_1v80.lib, FF_-40C_1v95.lib (Fast)

From: Stage 01 PDK Foundry

constraints.sdc + spef

Clock definitions, IO delays, timing exceptions, and extracted RC wire parasitics

From: Stages 01, 06, 08

⚙️ STA TIMING PROCESS

① SDC Parsing & Clock Groups

② PVT Library Characterization

③ Path Delay & Slew Propagation

④ Setup & Hold Slack Calculation

⑤ WNS & TNS Violation Diagnosis

⑥ ECO Gate Sizing & Signoff

↓

📤 OUTPUT FILES

timing_setup_ss.rpt

Critical path delay breakdown at worst-case SS corner showing arrival vs required times

→ Used by: Timing Closure & Signoff

timing_hold_ff.rpt

Hold time verification at best-case FF corner proving zero race conditions on fast paths

→ Used by: Hold Buffer Fix Flow

eco_timing_fixes.tcl

Engineering Change Order script with cell swap and buffer insertion commands

→ Used by: Physical Design Tool

📊 REPORTS / SIGNOFF

mcmm_wns_tns_matrix.rpt

Full PVT matrix signoff: WNS = +0.042 ns, TNS = 0.000 ns across all 12 operational modes

Signoff: Lead STA Engineer

drc_transition_slew.rpt

Electrical design rules check: Max transition < 0.20 ns and max capacitance met on all nets

Signoff: Signoff Review Board

SECTION 03 — REAL PROJECT WALKTHROUGH

PicoRV32 on SKY130: OpenSTA Signoff Timing Analysis

🔬 OPEN-SOURCE PROJECT

ProjectPicoRV32 Signoff STA on SkyWater 130nm

Slow Corner (SS)sky130_fd_sc_hd__ss_100C_1v60.lib (Max Delay)

Fast Corner (FF)sky130_fd_sc_hd__ff_n40C_1v95.lib (Min Delay)

Signoff SlackWNS = +0.042 ns (Setup), WHR = +0.184 ns (Hold)

STEP 1

OpenSTA Multi-Corner Execution Script (run_sta.tcl)

# OpenSTA Multi-Corner Timing Signoff Script for PicoRV32
read_liberty -corner slow sky130_fd_sc_hd__ss_100C_1v60.lib
read_liberty -corner fast sky130_fd_sc_hd__ff_n40C_1v95.lib

read_verilog picorv32_scan.v
link_design picorv32_top

# 1. Read SDC Timing Constraints and Back-Annotated SPEF Parasitics
read_sdc post_cts_constraints.sdc
read_spef -corner slow picorv32_rcmax.spef
read_spef -corner fast picorv32_rcmin.spef

# 2. Propagate real clock latencies & calculate slews
set_propagated_clock [all_clocks]

# 3. Report Setup and Hold Slacks
report_checks -corner slow -path_delay max -format full_clock_expanded -digits 4
report_checks -corner fast -path_delay min -format full_clock_expanded -digits 4
report_wns
report_tns

STEP 2

SDC Timing Exception Definitions (exceptions.sdc)

# SDC Timing Constraints & False Paths for PicoRV32
# 1. Primary Clock Definition
create_clock -name sys_clk -period 20.0 [get_ports clk]
set_clock_uncertainty -setup 0.40 [get_clocks sys_clk]
set_clock_uncertainty -hold  0.15 [get_clocks sys_clk]

# 2. Asynchronous Reset False Path (Static Signal)
set_false_path -from [get_ports resetn]

# 3. CDC Clock Group Isolation (Asynchronous Domains)
set_clock_groups -asynchronous \
    -group [get_clocks sys_clk] \
    -group [get_clocks rtc_clk]

# 4. Multicycle Path Definition for Hardware Multiplier (2 Cycles)
set_multicycle_path 2 -setup -from [get_pins u_core/alu/mult_a_reg*/CLK] -to [get_pins u_core/alu/mult_res_reg*/D]
set_multicycle_path 1 -hold  -from [get_pins u_core/alu/mult_a_reg*/CLK] -to [get_pins u_core/alu/mult_res_reg*/D]

STEP 3

Detailed Critical Path Setup Slack Report (sta_signoff.rpt)

=== OpenSTA Worst-Case Setup Timing Path Signoff ===
Corner      : slow (SS / 100°C / 1.60V)
Startpoint  : u_core/reg_pc[4] (rising edge-triggered flip-flop clocked by sys_clk)
Endpoint    : u_core/mem_addr_reg[12] (rising edge-triggered flip-flop clocked by sys_clk)
Path Type   : max (Setup Check)

  Pin                              Incr      Time
  --------------------------------------------------
  clock sys_clk (rise edge)        0.0000    0.0000
  clock network delay (propagated) 0.3842    0.3842
  u_core/reg_pc[4]/CLK             0.0000    0.3842 ^
  u_core/reg_pc[4]/Q (dfxtp_1)     0.4210    0.8052 ^
  u_core/alu/u_add/g24/Y (o21ai_1) 0.8420    1.6472 v
  u_core/alu/u_add/g88/Y (nand2_2) 0.5120    2.1592 ^
  u_core/mem_addr_reg[12]/D        0.2180   17.4820 ^ (Data Arrival Time)
  --------------------------------------------------
  clock sys_clk (rise edge)       20.0000   20.0000
  clock network delay (propagated) 0.4120   20.4120
  clock uncertainty               -0.4000   20.0120
  library setup time              -0.1280   19.8840
  data required time                        19.8840 (Data Required Time)
  --------------------------------------------------
  data required time                        19.8840
  data arrival time                        -17.4820
  --------------------------------------------------
  SLACK (MET)                              +2.4020 ns (PASS)

--- Full-Chip Timing Closure Summary ---
  Worst Negative Slack (WNS) : +0.0420 ns (PASS across all PVT corners)
  Total Negative Slack (TNS) :  0.0000 ns (0 Endpoints Violating)
  Worst Hold Slack (WHR)     : +0.1840 ns (FF Corner / -40°C PASS)
STATUS: STATIC TIMING ANALYSIS SIGNED OFF - ZERO TIMING VIOLATIONS

SECTION 04 — EDA TOOLS

Tools Used in Static Timing Analysis Stage

Static timing engines perform graph-based delay calculation, crosstalk glitch noise analysis, and automated Engineering Change Order (ECO) sizing.

Task	🏭 Synopsys	🔷 Cadence	🟧 Siemens EDA	🔓 Open-Source
Gold Standard Multi-Corner STA	Synopsys PrimeTime (PT / PT-SI)	Cadence Tempus Timing Signoff	Siemens Questa Timing (formerly Mentor)	OpenSTA
Signal Integrity (SI) Crosstalk Delay	Synopsys PrimeTime SI	Cadence Tempus SI	Siemens mPower Signal	OpenSTA (SI Mode)
Physically-Aware ECO Timing Repair	Synopsys PrimeClosure	Cadence Tempus ECO / Stylus	Siemens Aprisa Timing Closure	OpenROAD (repair_timing)
Advanced On-Chip Variation (AOCV/POCV)	Synopsys PrimeTime POCV	Cadence Tempus SSTA/POCV	Siemens Calibre YieldAnalyzer	OpenSTA (Derate modeling)
Timing Constraint Debug & Validation	Synopsys TimeGen / GConst	Cadence Conformal SDC	Siemens Questa SDC Check	OpenSTA `check_setup`