03Logic Synthesis

Logic Synthesis & Technology Mapping

The critical translation bridge from abstract behavioral code into physical silicon gates. Synthesis translates verified Verilog RTL into a technology-mapped gate-level netlist referencing the foundry's standard cell Liberty library (.lib) under strict Synopsys Design Constraints (SDC) — iteratively optimizing area, timing slack (WNS/TNS), and dynamic power consumption.

⏱️1–3 weeksTypical Duration

👥Logic Synthesis EngineerKey People

📄Gate Netlist (.v) + SDC + Synthesis QoRDeliverable

🔧Yosys, Design Compiler, GenusTool Phase

SECTION 01 — STAGE DESCRIPTION

What Happens in Logic Synthesis & Technology Mapping?

🧩 The Logic Synthesis Engineer's Job

RTL code describes what logical operations to perform, but provides zero information on which silicon transistors or standard cells to implement. Logic synthesis executes a multi-phase compilation pipeline: (1) Elaboration & Generic Technology (GTECH) — parsing behavioral Verilog into abstract Boolean logic equations and multiplexers; (2) High-Level Optimization — dead code elimination, constant folding, resource sharing across datapath ALUs, and state machine re-encoding; (3) Technology Mapping — replacing generic operators with actual characterized silicon standard cells (NAND, NOR, AND-OR-Invert AOI, XOR, DFF) from the foundry's Liberty (.lib) library.

During technology mapping, the synthesis engine continuously interacts with a built-in Static Timing Analysis (STA) solver. Given the customer's Synopsys Design Constraints (.sdc) specifying target clock frequencies (e.g. 50 MHz / 20.0 ns period) and I/O delays, the engine iteratively restructures high-fanout logic cones, swaps cell drive strengths (e.g. replacing `nand2_1` with high-drive `nand2_4`), and inserts buffer repeaters to meet setup timing requirements without violating area budgets.

The output of logic synthesis is a verified, technology-mapped Gate-Level Netlist (synthesis.v) along with comprehensive Quality-of-Results (QoR) reports detailing standard cell count, total silicon area (µm²), dynamic/leakage power dissipation, and pre-layout timing slack — ready for Formal Logic Equivalence Checking (03a) and Scan DFT Insertion (03b).

🏗️

Analogy: Like handing an architect's floorplan sketch (RTL) to a master structural engineer who selects exact steel I-beams, concrete pillars, and load-bearing masonry bricks from a specific manufacturer's catalog (.lib). The engineer calculates every structural load to ensure the building will never collapse under hurricane winds (timing constraints) while minimizing building materials cost (silicon area).

📋 What RTL & Spec Provide

Lint-clean, simulation-verified Verilog RTL
Liberty standard cell timing models (.lib)
Synopsys Design Constraints (.sdc)
UPF power intent (voltage domains & switches)
Foundry operating PVT corner definitions
Target Area (µm²) and Power (mW) budgets

📐 What the Synthesis Engineer Produces

Synthesized gate-level netlist (synthesis.v)
Synthesis Quality-of-Results (QoR) report
Pre-layout gate-level area & cell count breakdown
Pre-layout STA timing slack report (WNS/TNS)
Synthesis power dissipation estimate report
Netlist ready for Formal LEC (03a) & Scan (03b)

SECTION 02 — INPUT / OUTPUT FILES

Files Flow: Stage 03 Inputs & Outputs

📥 INPUTS

picorv32_top.v

Verified Verilog RTL source tree and module hierarchy from Stage 02/02b

From: Stage 02b BIST & JTAG

sky130_fd_sc_hd.lib

Liberty cell library — characterized delay tables (NLDM/CCS), pin capacitance, leakage power

From: Stage 01 PDK Foundry

constraints.sdc

Clock definitions (period, uncertainty), input/output delays, maximum transition limits

From: Stage 01 Architect

⚙️ STAGE 03 PROCESS

① RTL Elaboration & AST Parsing

② GTECH Generic Logic Synthesis

③ Boolean Algebra & Constant Folding

④ Technology Mapping to .lib Gates

⑤ Timing-Driven Gate Sizing

⑥ Pre-Layout QoR & Gate Netlist Export

↓

📤 OUTPUT FILES

picorv32_synthesis.v

Technology-mapped gate netlist containing 14,820 SKY130 standard cells

→ Used by: Stage 03a Formal LEC & 03b Scan

synth_constraints.sdc

Updated design constraints with synthesized clock definitions and internal cell delays

→ Used by: Floorplanning & Placement

synth_statistics.json

Machine-readable cell usage breakdown, gate counts per hierarchy, and pin density stats

→ Used by: Physical Design Team

📊 REPORTS / SIGNOFF

synthesis_qor.rpt

Quality-of-Results summary: 14,820 Gates, Area = 124,500 µm², Dynamic Power = 3.84 mW

Signoff: Lead Synthesis Engineer

pre_layout_timing.rpt

Zero-wireload STA report: WNS = +4.12 ns (Setup PASS @ 50 MHz), TNS = 0.00 ns

Signoff: Front-End Timing Lead

SECTION 03 — REAL PROJECT WALKTHROUGH

PicoRV32 on SKY130: Yosys Logic Synthesis

🔬 OPEN-SOURCE PROJECT

ProjectPicoRV32 RISC-V Synthesis on SkyWater 130nm

Standard Cells14,820 Gates (sky130_fd_sc_hd High-Density Library)

Die Core Area124,500 µm² (Pre-layout standard cell area)

Pre-Layout WNS+4.12 ns slack margin @ 50 MHz clock frequency

STEP 1

Yosys Synthesis TCL Script (synth_sky130.tcl)

# Yosys Synthesis Script for PicoRV32 on SkyWater 130nm
# 1. Read Verilog RTL Source
read_verilog -sv picorv32.v
hierarchy -check -top picorv32_top

# 2. Generic High-Level Boolean Optimization (GTECH)
proc; opt; fsm; opt; memory; opt

# 3. Technology Mapping to SkyWater 130nm Liberty Standard Cells
dfflibmap -liberty sky130_fd_sc_hd__tt_025C_1v80.lib
abc -liberty sky130_fd_sc_hd__tt_025C_1v80.lib \
    -constr picorv32_constraints.sdc \
    -D 20000

# 4. Clean up and export technology-mapped gate netlist
clean -purge
write_verilog -noattr picorv32_synthesis.v
stat -liberty sky130_fd_sc_hd__tt_025C_1v80.lib -json synth_stat.json

STEP 2

OpenSTA Pre-Layout Timing Verification Script

# OpenSTA Pre-Layout Zero-Wireload Timing Verification
read_liberty sky130_fd_sc_hd__tt_025C_1v80.lib
read_verilog picorv32_synthesis.v
link_design picorv32_top
read_sdc picorv32_constraints.sdc

# Report Pre-Layout Setup & Hold Timing
report_checks -path_delay max -format full_clock_expanded
report_wns
report_tns

STEP 3

Yosys Synthesis QoR & Cell Usage Report (synth_qor.rpt)

=== Yosys Synthesis Quality-of-Results: PicoRV32 ===
Target Technology : SkyWater SKY130 (sky130_fd_sc_hd)
Target Frequency  : 50.0 MHz (Clock Period = 20.00 ns)

--- Standard Cell Usage Breakdown ---
  sky130_fd_sc_hd__nand2_1   :  2,840 instances
  sky130_fd_sc_hd__nor2_1    :  1,420 instances
  sky130_fd_sc_hd__xor2_1    :    940 instances
  sky130_fd_sc_hd__a21oi_1   :  3,210 instances (Complex AOI Gates)
  sky130_fd_sc_hd__dfxtp_1   :  4,120 instances (Sequential DFFs)
  sky130_fd_sc_hd__buf_2     :  2,290 instances (Repeaters & Drivers)
  TOTAL STANDARD CELL COUNT  : 14,820 gates

--- Area & Power Metrics ---
  Total Standard Cell Area   : 124,500 µm² (0.1245 mm²)
  Estimated Dynamic Power    : 3.84 mW @ 50 MHz / 1.8V
  Estimated Leakage Power    : 0.18 mW

--- Pre-Layout Timing Slack ---
  Worst Negative Slack (WNS) : +4.12 ns (Setup PASS / 0 Violations)
  Total Negative Slack (TNS) :  0.00 ns
STATUS: STAGE 03 LOGIC SYNTHESIS COMPLETE - PROCEED TO FORMAL LEC & SCAN

SECTION 04 — EDA TOOLS

Tools Used in Logic Synthesis Stage

Logic synthesis engines parse hardware description code, solve Boolean satisfaction equations, and optimize gate topologies for maximum performance and minimum silicon area.

Task	🏭 Synopsys	🔷 Cadence	🟧 Siemens EDA	🔓 Open-Source
RTL Elaboration & Technology Mapping	Synopsys Design Compiler (DC / NXT)	Cadence Genus Synthesis Solution	Siemens Precision RTL Plus	Yosys Open SYnthesis Suite
Logic Cone Optimization & Gate Sizing	Synopsys DC Ultra / Topographical	Cadence Genus Optimizer	Siemens Precision Hi-Rel	ABC Logic Synthesis & Opt
Low-Power UPF Clock Gating Synthesis	Synopsys Power Compiler	Cadence Joules / Genus LP	Siemens PowerPro	Yosys (clock_gating pass)
Pre-Layout Zero-Wireload STA	Synopsys PrimeTime (Pre-Layout)	Cadence Tempus (Pre-Layout)	Siemens Questa Timing	OpenSTA
Physically-Aware Logic Synthesis	Synopsys Fusion Compiler	Cadence Genus Physical	Siemens Precision RTL Plus	OpenROAD Flow (Yosys+RePlAce)