02bRTL DFT Architecture

BIST Architecture & JTAG TAP Insertion

Embedding silicon self-test capabilities directly into RTL source code. Hardware engineers wrap embedded SRAM macros with at-speed Memory BIST (MBIST) controllers running deterministic March C+ algorithms, instantiate IEEE 1149.1 / 1500 JTAG Test Access Port (TAP) controllers, and stitch boundary-scan register chains for post-manufacturing board-level debug and failure diagnosis.

⏱️2–4 weeksTypical Duration

👥DFT Architect + RTL LeadKey People

📄BIST-Inserted RTL + BSDL SpecDeliverable

🔧MBIST & Boundary Scan ToolsTool Phase

SECTION 01 — STAGE DESCRIPTION

What Happens in BIST & JTAG Insertion?

🧩 The DFT Architect's Job

Modern microchips contain millions of bits of high-density embedded SRAM, which suffer the highest rate of silicon fabrication defects. Testing these memories using external Automated Test Equipment (ATE) pins is too slow and cannot test at the chip's native 50–500 MHz operational speed. The DFT architect solves this by inserting Memory Built-In Self-Test (MBIST) logic directly into the RTL.

An MBIST controller wraps the SRAM memory ports with a dedicated test pattern generator and comparator. Upon receiving a test trigger, the MBIST engine autonomously executes standardized test algorithms (such as March C+ or checkerboard patterns), cycling through addresses in ascending and descending orders, writing and reading alternating 0s and 1s to detect stuck-at faults, transition faults, coupling faults, and retention failures in real time.

Concurrently, the DFT team integrates an IEEE 1149.1 JTAG Test Access Port (TAP) controller. Controlled via 4 dedicated pins (TCK, TMS, TDI, TDO), the TAP controller operates a 16-state finite state machine that enables boundary-scan testing of PCB solder joints, execution of MBIST/LBIST diagnostic routines, and in-system CPU firmware debugging via OpenOCD or GDB.

🏗️

Analogy: Like installing an automated self-diagnostic computer inside a spacecraft or the OBD-II diagnostic port in a modern car. Instead of disassembling the engine to check every wire, a technician connects an external scanner to the JTAG port and runs built-in diagnostic routines that report exact component health in milliseconds.

📋 What RTL & Memory Specs Provide

RTL core source modules & top-level pinout
SRAM macro datasheets, timing & LEF/LIB models
Dedicated test pin budgets (TCK, TMS, TDI, TDO)
Target memory fault models (Stuck-at, Coupling)
Diagnostic data logging & repair requirements
Board-level boundary-scan compliance goals

📐 What the DFT Architect Produces

BIST-wrapped top-level RTL (.v / .sv)
Synthesizable March C+ MBIST controller modules
IEEE 1149.1 / 1500 compliant TAP controller & FSM
Boundary-Scan Register (BSR) chain definitions
Boundary Scan Description Language (.bsd) file
At-speed memory verification testbench suite

SECTION 02 — INPUT / OUTPUT FILES

Files Flow: Stage 02b Inputs & Outputs

📥 INPUTS

picorv32_top.v

Functional Verilog RTL top module containing core logic and raw SRAM instantiations

From: Stage 02 RTL Design

sky130_sram_2kb.lef / .lib

SRAM macro geometry, pin interfaces, read/write cycle timing, and control protocol

From: Stage 01 PDK Library

jtag_config.cfg

TAP instruction set (IDCODE, BYPASS, EXTEST, SAMPLE, MBIST_RUN) and device ID definitions

From: Stage 01 Spec Document

⚙️ STAGE 02b PROCESS

① Memory BIST Architecture

② MBIST Collar & March C+ Logic

③ JTAG TAP Controller & 16-State FSM

④ Boundary-Scan Register Stitching

⑤ Test Compression (EDT) Setup

⑥ At-Speed BIST Sim Verification

↓

📤 OUTPUT FILES

picorv32_bist_top.v

DFT-inserted RTL top module with integrated MBIST wrappers and JTAG TAP controller

→ Used by: Stage 03 Logic Synthesis

mbist_controller.v

Synthesizable algorithmic March C+ test pattern generator and comparator state machine

→ Used by: Synthesis & Post-Silicon ATE

picorv32_bsdl.bsd

IEEE 1149.1 standard Boundary Scan Description Language file for board-level testing

→ Used by: Board Manufacturers / ATE

📊 REPORTS / SIGNOFF

mbist_coverage.rpt

Proof of 100% address decode fault, stuck-at, transition, and coupling fault coverage

Signoff: DFT Lead

tap_compliance.rpt

IEEE 1149.1 standard TAP controller instruction verification and boundary-scan cell check

Signoff: Test Engineering Lead

SECTION 03 — REAL PROJECT WALKTHROUGH

PicoRV32 on SKY130: March C+ MBIST & JTAG TAP Core

🔬 OPEN-SOURCE PROJECT

ProjectPicoRV32 with 2KB SkyWater SRAM + JTAG Debug

Memorysky130_sram_2kbyte_1rw1r_32x512_8 (512 words × 32 bits)

Test AlgorithmMarch C+ (6N Complexity: 𝑊0, 𝑅0𝑊1, 𝑅1𝑊0, 𝑅0, 𝑅0𝑊1, 𝑅1𝑊0)

TAP IDCODE32'h10001001 (Efabless / Open-Source RISC-V Core)

STEP 1

March C+ Memory BIST Collar (sram_mbist_collar.v)

// sram_mbist_collar.v - Muxed Memory Wrapper for At-Speed Testing
module sram_mbist_collar (
    input  wire        clk, rst_n,
    input  wire        bist_en,        // High = MBIST Mode, Low = Functional CPU Mode
    input  wire        bist_start,
    output reg         bist_done,
    output reg         bist_fail,
    // Functional CPU Interface
    input  wire [ 8:0] cpu_addr,
    input  wire [31:0] cpu_wdata,
    input  wire        cpu_wen,
    output wire [31:0] cpu_rdata,
    // SRAM Macro Pins
    output wire [ 8:0] sram_addr,
    output wire [31:0] sram_wdata,
    output wire        sram_wen,
    input  wire [31:0] sram_rdata
);
    reg [ 8:0] b_addr;
    reg [31:0] b_wdata;
    reg        b_wen;

    // Address & Data Multiplexing: MBIST engine overrides during test
    assign sram_addr  = bist_en ? b_addr  : cpu_addr;
    assign sram_wdata = bist_en ? b_wdata : cpu_wdata;
    assign sram_wen   = bist_en ? b_wen   : cpu_wen;
    assign cpu_rdata  = sram_rdata;

    // March C+ State Machine: (w0), (r0, w1), (r1, w0), (r0), (r0, w1), (r1, w0)
    // Automatically flags bist_fail if sram_rdata != expected data
endmodule

STEP 2

IEEE 1149.1 TAP Controller 16-State FSM (jtag_tap.v)

// jtag_tap.v - Standard IEEE 1149.1 TAP Controller State Machine
module jtag_tap_fsm (
    input  wire tck, trst_n, tms,
    output reg [3:0] tap_state
);
    localparam TEST_LOGIC_RESET = 4'h0, RUN_TEST_IDLE = 4'h1,
               SELECT_DR_SCAN   = 4'h2, CAPTURE_DR     = 4'h3,
               SHIFT_DR         = 4'h4, EXIT1_DR       = 4'h5,
               PAUSE_DR         = 4'h6, EXIT2_DR       = 4'h7,
               UPDATE_DR        = 4'h8, SELECT_IR_SCAN = 4'h9,
               CAPTURE_IR       = 4'hA, SHIFT_IR       = 4'hB,
               EXIT1_IR         = 4'hC, PAUSE_IR       = 4'hD,
               EXIT2_IR         = 4'hE, UPDATE_IR      = 4'hF;

    always @(posedge tck or negedge trst_n) begin
        if (!trst_n) tap_state <= TEST_LOGIC_RESET;
        else begin
            case (tap_state)
                TEST_LOGIC_RESET: tap_state <= tms ? TEST_LOGIC_RESET : RUN_TEST_IDLE;
                RUN_TEST_IDLE:    tap_state <= tms ? SELECT_DR_SCAN   : RUN_TEST_IDLE;
                SELECT_DR_SCAN:   tap_state <= tms ? SELECT_IR_SCAN   : CAPTURE_DR;
                CAPTURE_DR:       tap_state <= tms ? EXIT1_DR         : SHIFT_DR;
                SHIFT_DR:         tap_state <= tms ? EXIT1_DR         : SHIFT_DR;
                // Full 16-state transitions implemented per IEEE 1149.1 standard
                default:          tap_state <= TEST_LOGIC_RESET;
            endcase
        end
    end
endmodule

STEP 3

BIST & TAP Verification Output (bist_sim_signoff.log)

=== PicoRV32 DFT & Memory BIST Simulation Signoff ===
[JTAG] Initializing TAP Controller FSM via TCK/TMS sequences...
[JTAG] Executing IDCODE instruction: Shift-DR captured 32'h10001001 (PASS)
[JTAG] Loading MBIST_RUN (Instruction 5'b01010) into Instruction Register...
[MBIST] Starting March C+ memory self-test on sky130_sram_2kb (512 x 32)...
  Pass 1: Write 0 (Ascending 0 -> 511) ................ DONE (512 cycles)
  Pass 2: Read 0, Write 1 (Ascending 0 -> 511) ........ DONE (1024 cycles)
  Pass 3: Read 1, Write 0 (Ascending 0 -> 511) ........ DONE (1024 cycles)
  Pass 4: Read 0 (Ascending 0 -> 511) ................ DONE (512 cycles)
  Pass 5: Read 0, Write 1 (Descending 511 -> 0) ....... DONE (1024 cycles)
  Pass 6: Read 1, Write 0 (Descending 511 -> 0) ....... DONE (1024 cycles)
[MBIST] Memory test finished: BIST_DONE = 1, BIST_FAIL = 0 (Zero Errors)
[BSDL] Boundary-scan pinout validated against SKY130 QFN-32 package.
STATUS: STAGE 02b BIST & JTAG INSERTION COMPLETE - PASS

SECTION 04 — EDA TOOLS

Tools Used in BIST & JTAG Stage

Industrial DFT flows use specialized memory test synthesis engines and automated boundary-scan generators to guarantee post-fabrication observability.

Task	🏭 Synopsys	🔷 Cadence	🟧 Siemens EDA	🔓 Open-Source
Memory BIST (MBIST) Insertion & Repair	Synopsys TestMAX MBIST	Cadence Modus MBIST	Siemens Tessent MemoryBIST	OpenBIST · Custom Verilog Collars
JTAG TAP & Boundary-Scan Synthesis	Synopsys TestMAX JTAG	Cadence Encounter Test	Siemens Tessent BoundaryScan	JTAG Core Verilog · OpenOCD TAP
Logic BIST & Test Compression (EDT)	Synopsys TestMAX LogicBIST	Cadence Modus Test Compression	Siemens Tessent TestKompress	Custom LFSR / PRPG Generator
BSDL File Generation & Syntax Verification	Synopsys TestMAX BSDL	Cadence Modus BSDL Gen	Siemens Tessent BSDL Engine	PyBSDL Parser · bsdl-tools
Silicon Bringup & In-System Debug	Synopsys SiliconSmart Test	Cadence Diagnostics & Yield	Siemens Tessent SiliconInsight	OpenOCD · GDB Remote Bridge