03bScan & Testability

Scan Chain Insertion & ATPG Test Generation

Engineering manufacturing silicon testability directly into gate netlists. Scan synthesis replaces standard D-Flip-Flops with multiplexed Scan Flip-Flops (SDFF), stitches serial scan chains across clock domains, and Automatic Test Pattern Generation (ATPG) computes compact test vector sets detecting >99% stuck-at and transition delay manufacturing defects on ATE testers.

⏱️1–2 weeksTypical Duration

👥DFT & Testability EngineerKey People

📄Scan Netlist + SCANDEF + ATPG STILDeliverable

🔧Fault, TetraMAX, TessentTool Phase

SECTION 01 — STAGE DESCRIPTION

What Happens in Scan Insertion & ATPG?

🧩 The DFT & Testability Engineer's Job

Once a microchip is fabricated, billions of internal transistors are buried beneath multiple interconnect metal layers with zero physical probe access. Microscopic manufacturing defects — such as airborne dust particles causing metal bridges, voided vias causing open circuits, or gate oxide pinholes — cause transistors to remain permanently stuck at logic '0' or logic '1'. Design-for-Testability (DFT) builds dedicated test hardware directly into the digital gate netlist to expose these silicon flaws.

Scan insertion replaces every functional D-Flip-Flop with a multiplexed Scan Flip-Flop (SDFF). When the Scan Enable (SE) control pin is asserted, all flip-flops decouple from functional logic and connect serially as a massive shift register (Scan Chain). Test vectors are shifted into the chip via Scan In (SI) pins, the system clock is pulsed for one cycle in capture mode to exercise combinational logic, and the captured response is shifted out via Scan Out (SO) pins for comparison against golden simulator vectors.

The Automatic Test Pattern Generation (ATPG) software analyzes netlist topology using algorithms (such as the D-Algorithm and PODEM) to calculate the smallest set of test patterns that achieves >99.0% Stuck-At Fault Coverage and at-speed Transition Delay Fault Coverage. Compact pattern sets minimize test time on multi-million-dollar Automated Test Equipment (ATE) tester machines, driving down per-die production costs.

🏗️

Analogy: Like installing an onboard diagnostic (OBD-II) port and automated sensors throughout an aircraft engine. Instead of dismantling the entire jet engine after every flight to check each turbine blade (dynamic simulation), a technician plugs an external diagnostic scanner into the OBD port, runs a 3-second automated test sequence, and immediately identifies the exact sensor with an electrical fault.

📋 What Synthesis & LEC Provide

Synthesized technology-mapped netlist (synthesis.v)
Foundry scan cell Liberty library (.lib)
Test clock & asynchronous reset pin definitions
Asynchronous clock domain definitions
Memory BIST and JTAG boundary scan collar
Formal logic equivalence verification pass

📐 What the DFT Engineer Produces

Scan-inserted gate netlist (picorv32_scan.v)
SCANDEF physical order constraint file for placement
ATPG manufacturing test vectors (STIL / WGL format)
Stuck-at fault coverage report (> 99% coverage)
Transition delay fault coverage report
Scan DRC rule check report (0 controllability errors)

SECTION 02 — INPUT / OUTPUT FILES

Files Flow: Stage 03b Inputs & Outputs

📥 INPUTS

picorv32_synthesis.v

Unmapped technology gate netlist produced by synthesis and validated by LEC

From: Stage 03 Logic Synthesis

sky130_fd_sc_hd__scan.lib

Liberty timing library defining multiplexed scan flip-flop cells (sdfrtp_1, sdfbbp_1)

From: Stage 01 PDK Foundry

dft_constraints.tcl

DFT specification: scan chain count (8 chains), test clock frequency, and scan pin mapping

From: Stage 01 System Architecture

⚙️ STAGE 03b PROCESS

① Scan Cell Substitution (DFF → SDFF)

② Clock Domain Chain Stitching

③ Scan DRC Rule Verification

④ SCANDEF Constraint Generation

⑤ ATPG Fault Model Simulation

⑥ Test Coverage & STIL Export

↓

📤 OUTPUT FILES

picorv32_scan.v

Gate netlist with 4,120 Scan-Mux DFFs stitched into 8 balanced serial scan chains

→ Used by: Stage 04 Floorplan & 05 Placement

picorv32_scan.def (SCANDEF)

Scan chain connectivity and cell ordering constraints to minimize wire cross-over during placement

→ Used by: Stage 05 Placement Suite

picorv32_patterns.stil

Standard Test Interface Language (IEEE 1450 STIL) binary vector patterns for ATE test floor

→ Used by: ATE Foundry Test Engineering

📊 REPORTS / SIGNOFF

atpg_coverage_summary.rpt

Stuck-At Fault Coverage: 99.42% (> 99.0% Target PASS), Transition Delay: 96.8%

Signoff: Lead DFT Test Engineer

scan_drc_check.rpt

DFT rule check: 0 clock controllability violations, 0 reset glitches, 100% scan shift valid

Signoff: Design Verification Lead

SECTION 03 — REAL PROJECT WALKTHROUGH

PicoRV32 on SKY130: Fault Scan Insertion & ATPG

🔬 OPEN-SOURCE PROJECT

ProjectPicoRV32 Scan Insertion & ATPG on SKY130

Scan Cells4,120 Scan Flip-Flops stitched across 8 chains

Stuck-At Coverage99.42% (Target > 99.0% met with 0.42% margin)

Test Pattern Count1,420 ATE Test Vector Cycles (< 2s per chip)

STEP 1

Open-Source Fault Scan Insertion Command

# Fault Scan Chain Insertion for PicoRV32
fault \
    -liberty sky130_fd_sc_hd__tt_025C_1v80.lib \
    -netlist picorv32_synthesis.v \
    -scan-chain-count 8 \
    -clock clk \
    -reset rst_n \
    -output-netlist picorv32_scan.v \
    -output-scandef picorv32_scan.def

STEP 2

Fault ATPG Test Vector Generation Execution

# Fault Automatic Test Pattern Generation (ATPG)
fault-atpg \
    -liberty sky130_fd_sc_hd__tt_025C_1v80.lib \
    -netlist picorv32_scan.v \
    -output-vectors picorv32_atpg.stil \
    -fault-model stuck-at \
    -effort high \
    -report-file atpg_coverage_summary.rpt

STEP 3

ATPG Fault Coverage & Test Vector Signoff (atpg_signoff.rpt)

=== Fault ATPG Test Coverage Signoff: PicoRV32 ===
Design Top     : picorv32_top
Target PDK     : SkyWater SKY130 (130nm Standard Cells)

--- Scan Architecture Summary ---
  Total Flip-Flops Placed   : 4,120 cells
  Scan Chains Inserted      : 8 chains (Chain length: ~515 flip-flops/chain)
  Dedicated Scan Pins       : 8 SI pins, 8 SO pins, 1 Scan-Enable (SE) pin
  Scan DRC Status           : 0 Violations (PASS - All clocks & resets controlled)

--- ATPG Fault Coverage Statistics ---
  Total Collapsed Faults    : 48,240 faults
  Detected Faults (DT)      : 47,960 faults
  Untestable Faults (UT)    :    180 faults (Tied pins / redundant logic)
  Undetected Faults (UD)    :    100 faults
  STUCK-AT FAULT COVERAGE   : 99.42% (PASS / Exceeds 99.00% Foundry Signoff)
  Total Test Patterns       : 1,420 vectors
  Estimated ATE Test Time   : 1.42 ms @ 10 MHz shift frequency
STATUS: STAGE 03b SCAN INSERTION & ATPG COMPLETE - PASS

SECTION 04 — EDA TOOLS

Tools Used in Scan Insertion & ATPG Stage

Industrial DFT and ATPG tool suites automate scan synthesis, test data compression (EDT), and fault modeling for multi-million-gate system-on-chips.

Task	🏭 Synopsys	🔷 Cadence	🟧 Siemens EDA	🔓 Open-Source
Scan Cell Replacement & Chain Stitching	Synopsys DFTMAX / DFT Compiler	Cadence Genus DFT	Siemens Tessent Scan	Fault (Scan Engine) · Yosys
Automatic Test Pattern Generation (ATPG)	Synopsys TetraMAX ATPG	Cadence Modus ATPG	Siemens Tessent FastScan	Fault ATPG · Atalanta
At-Speed Transition Delay Fault ATPG	Synopsys TetraMAX Delay ATPG	Cadence Modus Delay ATPG	Siemens Tessent Transition	Fault (Delay Model)
Test Compression (EDT / AdaptiveScan)	Synopsys DFTMAX Compression	Cadence Modus Compression	Siemens Tessent TestKompress	Fault (Channel Mux)
ATE Tester Vector Formatting (STIL / WGL)	Synopsys TestMAX Manager	Cadence Modus Vector Formatter	Siemens Tessent SiliconInsight	Fault (write_stil / write_wgl)