STA-MAXMax Delay Signoff

Setup Slack & Maximum Delay Closure

The definitive mathematical and silicon-level guide to Setup Time verification in digital VLSI. Setup timing guarantees that logic transitions through complex combinational networks settle into a stable state before the capturing register samples data, preventing metastability and guaranteeing functional correctness at target clock frequencies.

🎯WNS ≥ 0.00 ns, TNS = 0.00 nsSignoff Criterion

❄️Slow-Slow (SS) CornerWorst-Case PVT

🔋Low VDD (0.90 × V_nom), 125°CThermal/Voltage

🛠️Upsizing, LVT swap, Useful SkewECO Remediation

SECTION 01 — SILICON PHYSICS

Why Setup Time Exists in CMOS Master-Slave Flip-Flops

🔬 The Transistor-Level Physics of Latching

At the physical silicon layer, an edge-triggered D flip-flop (DFF) consists of two cascaded stages: a Master Latch and a Slave Latch, controlled by complementary clock phases generated by an internal clock inverter (CLK and CLK_BAR).

For the master latch to safely store the incoming data bit D, the internal transmission gate (TG1) must transmit the voltage onto the storage node (N1), and the cross-coupled inverter feedback loop (I1 / I2) must regenerate and develop a stable regenerative differential voltage before the active clock edge shuts TG1 OFF.

Definition of Setup Time (Tsetup): The minimum duration before the active clock edge during which the data input D must remain stable and unchanged. Mathematically, it equals the propagation delay through the input transmission gate plus the time required for internal regenerative feedback to lock the state:T_setup = t_pd(TG1) + t_regen(I1/I2) - t_clk_to_tg1_off

💥 What Happens if Data Violates Setup Time? (Metastability)

If data transitions too close to the clock edge (within the setup window), the transmission gate begins turning off while the node is at an intermediate voltage (e.g. V_DD / 2). The back-to-back inverters enter a metastable state where both NMOS and PMOS transistors operate simultaneously in saturation, causing an indeterminate delay before resolving randomly to '0' or '1'. This causes catastrophic downstream glitches and system crashes.

📐 Master-Slave DFF Topology

CLK = 0: Master is Transparent, Slave is Latched.
CLK = 1 (Rising Edge): Master latches N1 → QM; Slave becomes transparent and drives Q.

SECTION 02 — REGISTER-TO-REGISTER MAX DELAY PATH

Interactive Setup Timing Path & Waveforms Sandbox

Adjust any timing parameter or select a scenario preset below. The aligned timing waveforms, data arrival transition envelope, clock edges, setup sampling window (T_setup), and Slack margin will dynamically redraw in real time.

CIRCUIT TOPOLOGY

Launch-to-Capture Timing Path Architecture

✅

LIVE SETUP SLACK MARGIN

+2.35 ns (MET)

Arrival Time (T_arr):7.25 ns

Required Time (T_req):9.60 ns

Clock Period:10.00 ns

🎉 Timing Met: Data finishes switching at 7.25 ns, well before the required sampling threshold of 9.60 ns. Capture flop samples clean digital '1' with +2.35 ns margin.

⏱️ Dynamic Aligned Timing Waveforms (Live Rendered)

Interactive Real-Time SVG

SECTION 03 — MATHEMATICAL FORMULATION

Exact Mathematical Formulations for Setup Slack

FUNDAMENTAL STA MODEL

1. Classical Setup Timing Formulations

In standard Static Timing Analysis, Setup is evaluated at the next clock edge (1 clock period later, T_period):

Data Arrival Time (T_arrival, max)

T_arrival = T_launch_clk + T_cq_max + T_comb_max

Where T_{comb_max} = Σ(t_gate_delay + t_net_delay).

Data Required Time (T_required, max)

T_required = T_period + T_capture_clk - T_setup - T_uncertainty

Where T_uncertainty = t_jitter + t_clock_tree_skew + t_margin.

Setup Slack Formulation
Slack_setup = T_required - T_arrival ≥ 0.00 ns
A positive slack (≥ 0) indicates timing closure; negative slack (< 0) is a timing violation.

ADVANCED VARIATION MODEL

2. On-Chip Variation (OCV / POCV) & Clock Skew

In modern FinFET nodes (16nm down to 3nm), process, voltage, and temperature variations occur across the die. STA tools apply derate factors and Clock Path Pessimism Removal (CPPR):

Setup Slack with OCV Derates & CPPR

Slack_setup = (T_period + T_capt_clk_min - T_setup - T_unc + CPPR) - (T_lnch_clk_max + T_cq_max + T_comb_max)

Clock Skew (ΔT_skew) Influence on Setup

T_skew = T_capture_clk - T_launch_clk

Positive Skew (T_skew > 0): Capture clock arrives after launch clock. Helps Setup timing by expanding the available time window!
Negative Skew (T_skew < 0): Capture clock arrives before launch clock. Harms Setup timing and shrinks allowable combinational delay.

Multi-Cycle Path Formulation

T_required = (N × T_period) + T_capture_clk - T_setup - T_uncertainty

Specified via SDC: set_multicycle_path 2 -setup -from [get_pins FF1/CLK] -to [get_pins FF2/D]

SECTION 04 — SIGN-OFF ARTIFACTS

Annotated Real-World OpenSTA Setup Timing Report

Here is a real report generated by OpenSTA for a 32-bit RISC-V core (`picorv32`) on the SkyWater 130nm PDK at the Slow-Slow corner (100°C, 1.60V):

timing_setup_ss_100C_1v60.rptOpenSTA v2.5 / Sky130 HD

================================================================================
Path 1: MET Setup Check
Endpoint:   _14208_ (sky130_fd_sc_hd__dfxtp_1 clocked by clk)
Path Group: clk
Path Type:  max (Setup Check)
Corner:     slow (SS_100C_1v60)
================================================================================

  Fanout     Cap    Slew    Delay     Time   Description
--------------------------------------------------------------------------------
                     0.00    0.00     0.00   clock clk (rise edge)
                             0.00     0.00   clock network delay (ideal)
       1    0.02     0.18    0.28     0.28 ^ clk_buf_1/X (sky130_fd_sc_hd__clkbuf_16)
       1    0.01     0.12    0.19     0.47 ^ _12984_/CLK (sky130_fd_sc_hd__dfxtp_1)
                             0.38     0.85 v _12984_/Q (sky130_fd_sc_hd__dfxtp_1)  <-- T_cq delay
       3    0.04     0.24    0.42     1.27 ^ _08231_/Y (sky130_fd_sc_hd__nand2_2)
       2    0.03     0.31    0.58     1.85 v _08232_/Y (sky130_fd_sc_hd__o21ai_2)
       4    0.08     0.45    0.92     2.77 ^ _09412_/Y (sky130_fd_sc_hd__a21oi_1)
       8    0.15     0.62    1.48     4.25 v _11029_/Y (sky130_fd_sc_hd__mux2_2)
       1    0.02     0.22    0.41     4.66 ^ _14208_/D (sky130_fd_sc_hd__dfxtp_1)
--------------------------------------------------------------------------------
                                      4.66   data arrival time

                            10.00    10.00   clock clk (rise edge next cycle)
                             0.00    10.00   clock network delay (ideal)
       1    0.02     0.16    0.26    10.26 ^ clk_buf_2/X (sky130_fd_sc_hd__clkbuf_16)
                             0.18    10.44 ^ _14208_/CLK (sky130_fd_sc_hd__dfxtp_1)
                            -0.25    10.19   clock uncertainty                      <-- Jitter / Margin
                            -0.34     9.85   cell setup time                        <-- T_setup Library
--------------------------------------------------------------------------------
                                      9.85   data required time
--------------------------------------------------------------------------------
                                      9.85   data required time
                                     -4.66   data arrival time
--------------------------------------------------------------------------------
                                      +5.19   slack (MET)

SECTION 05 — SILICON ECO PLAYBOOK

How to Fix Setup Timing Violations

🚀

1. Gate Upsizing (Drive Strength)

Replace high-impedance logic gates with larger drive strength cells (e.g. `nand2_1` → `nand2_4` or `nand2_8`). Decreases output cell delay and sharpens output transition slew on high capacitive nets.

size_cell -cell _09412_ sky130_fd_sc_hd__a21oi_4

🔄

2. Multi-Vt Swapping (HVT → LVT)

Swap High-Threshold Voltage (HVT) transistors for Low-Threshold Voltage (LVT) or Extra-Low-Vt (eLVT) cells. LVT gates switch ~25-35% faster at the cost of higher sub-threshold leakage power.

swap_vt -cells [get_cells -of $critical_path] -to LVT

🪵

3. Logic Restructuring & Buffer Insertion

Break up long combinational logic chains by cloning high-fanout drivers, restructuring multi-input boolean expressions, or inserting intermediate pipeline registers (retiming).

insert_buffer -net data_bus_31 sky130_fd_sc_hd__buf_8

⏱️

4. Useful Clock Skew Scheduling

Intentionally delay the clock arrival at the capturing register (T_{capture_clk} ↑) by adding delay buffers in the CTS branch, borrowing time from adjacent downstream stages that have positive slack.

set_clock_skew_target -cell FF_REG2 -skew +0.35ns

🛣️

5. Metal Layer Promotion (Routing)

Promote critical signal nets from high-resistance lower metal layers (Metal 1-3) to thick, low-RC top metal layers (Metal 4-6), reducing interconnect RC propagation delay.

set_net_routing_rule -nets [get_nets $crit_net] -layer M5_M6

📉

6. Frequency Derating (Last Resort)

If physical silicon cannot be closed at target frequency due to logic depth limitations, derate clock period (e.g. 500MHz → 400MHz). Setup timing relaxes linearly with clock period!

create_clock -period 2.50 [get_ports clk] # 400MHz

COMPLEMENTARY TIMING CHECK

Explore Hold Slack & Minimum Delay Analysis

While Setup violations can be avoided by relaxing clock speed, Hold violations are fatal in silicon and cannot be fixed after fabrication. Learn why Hold is frequency-independent and how to insert hold buffers safely.

Explore Hold Slack Deep Dive Return to STA Overview