05Physical Placement

Standard Cell Placement & Decap/Filler Suite

Physically positioning every standard cell from the gate-level netlist onto legalized silicon rows. Analytical electrostatics-driven global placers minimize Half-Perimeter Wirelength (HPWL) and routing congestion, legalizers eliminate cell overlaps, decoupling capacitors (Decaps) absorb dynamic power switching noise, and standard cell fillers guarantee 100% continuous N-well substrate biasing.

⏱️1–3 weeksTypical Duration

👥Physical Design EngineerKey People

📄Placed & Filled DEF + Post-Place STADeliverable

🔧Global Placer, Legalizer, Filler GenTool Phase

SECTION 01 — STAGE DESCRIPTION

What Happens in Standard Cell Placement?

🧩 The Placement Engineer's Job

The gate netlist describes which cells connect together, but provides zero physical (X,Y) coordinates. Placement solves a massive constrained optimization problem in three distinct steps: (1) Global Placement, (2) Detailed Placement & Legalization, and (3) Decap & Filler Cell Insertion.

During global placement, algorithms (such as RePlAce or ePlace) model standard cells as charged particles in an electrostatic field. Connected nets exert attractive spring forces to minimize total wirelength (Half-Perimeter Wirelength, HPWL), while an electric repulsion field forces cells to spread uniformly across standard cell rows, preventing hot spots and routing congestion.

During detailed placement, legalizers snap cell coordinates to exact standard cell row boundaries (2.72 µm pitch in SKY130) and resolve all overlapping gates. Once legal, Decoupling Capacitors (Decaps) are inserted into empty gaps to serve as local charge reservoirs during high-frequency clock switching (suppressing L · di/dt power noise). Finally, Cell Fillers are added to ensure the N-well diffusion layers remain continuous across the die to eliminate latch-up risks. Post-placement Static Timing Analysis (STA) verifies timing slack with estimated physical wirelengths.

🏗️

Analogy: Like packing fragile items into a moving truck (spring physics meets Tetris). Items that belong together in the same room are placed close to minimize walking distance (HPWL), heavy items are strictly aligned to floor slots without overlapping (legalization), and empty spaces are stuffed with shock-absorbing foam padding (Decaps) to absorb road bumps.

📋 What Floorplan & Netlist Provide

Floorplan DEF with PDN straps & macros
Scan-stitched gate netlist (synthesis_scan.v)
Standard cell physical LEF models (cell height/width)
Liberty timing libraries (.lib) for timing-driven flow
Decap and filler cell library definitions
SDC timing constraints for path delay budgeting

📐 What the Placement Engineer Produces

Legalized placed DEF file (zero cell overlaps)
Fully filled DEF with Decaps & standard fillers
Global routing congestion heatmap (0.00% overflow)
Total Half-Perimeter Wirelength (HPWL) statistics
100% continuous N-well & substrate tap signoff
Post-placement STA timing report (WNS & TNS)

SECTION 02 — INPUT / OUTPUT FILES

Files Flow: Stage 05 Inputs & Outputs

📥 INPUTS

picorv32_pdn.def

Floorplan DEF containing die boundary, core site rows, IO pins, and synthesized PDN power mesh

From: Stage 04 Floorplan Suite

picorv32_scan.v

Scan-inserted gate netlist containing 14,820 standard cells to be assigned physical (X,Y) coordinates

From: Stage 03 Logic Synthesis

sky130_fd_sc_hd.lef / .lib

Cell geometry and characterized timing models used to guide timing-driven cell clustering

From: Stage 01 PDK Library

⚙️ STAGE 05 PROCESS

① Global Electrostatic Placement

② Congestion Map Evaluation

③ Detailed Placement & Legalization

④ Decoupling Capacitor Insertion

⑤ Standard Cell Filler Insertion

⑥ Post-Placement STA Sign-off

↓

📤 OUTPUT FILES

picorv32_placed.def

Legalized placement DEF file with all standard cells snapped to site rows without overlaps

→ Used by: Post-Place STA & Fillers

picorv32_filled.def

Fully stuffed core area containing Decap capacitors and filler cells for 100% N-well continuity

→ Used by: Stage 06 CTS Suite

congestion_heatmap.png

Visual 2D routing congestion heatmap verifying that edge capacities are not exceeded

→ Used by: Routing Feasibility Review

📊 REPORTS / SIGNOFF

post_placement_sta.rpt

Timing analysis report based on estimated wirelengths: WNS = +1.84 ns (0 setup violations)

Signoff: Timing Signoff Lead

placement_density.rpt

Core utilization (68.4%), total HPWL (4.12 m), cell overlap count = 0 (PASS)

Signoff: Physical Design Lead

SECTION 03 — REAL PROJECT WALKTHROUGH

PicoRV32 on SKY130: RePlAce Placement & Decap Fill

🔬 OPEN-SOURCE PROJECT

ProjectPicoRV32 Standard Cell Placement Suite

Instance Count14,820 standard cells + 1,240 filler cells

HPWL Wirelength4.12 meters (Half-Perimeter Wirelength)

Decap Capacitance4.2 pF total integrated decoupling capacitance

STEP 1

OpenROAD Global Placement TCL Script (placement.tcl)

# OpenROAD Global Placement Execution
read_def picorv32_pdn.def
read_sdc picorv32_constraints.sdc

# 1. Global Analytical Placement (Electrostatic ePlace engine)
global_placement \
    -density 0.68 \
    -overflow 0.10 \
    -pad_left 2 \
    -pad_right 2 \
    -timing_driven \
    -routability_driven

# 2. Check estimated HPWL & routing congestion
estimate_parasitics -placement
report_checks -path_delay max -format full_clock_expanded

STEP 2

Detailed Legalization & Decap/Filler Insertion Script

# 1. Legalize cell placement onto standard cell rows
detailed_placement
check_placement -verbose

# 2. Insert Decoupling Capacitors (Decaps) for Power Noise Suppression
filler_placement \
    -cells "sky130_fd_sc_hd__decap_12 sky130_fd_sc_hd__decap_8 sky130_fd_sc_hd__decap_4" \
    -prefix "DECAP_"

# 3. Fill remaining row gaps with standard filler cells for N-well continuity
filler_placement \
    -cells "sky130_fd_sc_hd__fill_8 sky130_fd_sc_hd__fill_4 sky130_fd_sc_hd__fill_2 sky130_fd_sc_hd__fill_1" \
    -prefix "FILLER_"

# 4. Export finalized placement DEF
write_def picorv32_filled.def

STEP 3

Placement Signoff & Post-Place STA Report (placement_signoff.rpt)

=== OpenROAD Placement & Filler Signoff: PicoRV32 ===
Target Die Area : 300.00 µm x 300.00 µm (Core: 260.00 µm x 260.00 µm)

--- Placement Quality of Results (QoR) ---
  Standard Cells Placed        : 14,820 instances
  Decap Capacitor Cells Added  :    340 instances (4.2 pF total capacitance)
  Standard Filler Cells Added  :  1,240 instances
  Total Placed Cell Count      : 16,400 instances
  Half-Perimeter Wirelength    : 4.12 meters (HPWL)
  Cell Overlap Count           : 0 (100% LEGALIZED)
  N-Well Continuity Check      : PASS (Zero substrate gaps)

--- Post-Placement Static Timing Analysis ---
  Clock sys_clk Target Period  : 20.00 ns (50.0 MHz)
  Worst Critical Path Delay    : 17.65 ns
  Worst Negative Slack (WNS)   : +2.35 ns (Setup Timing Met)
  Total Negative Slack (TNS)   :  0.00 ns
STATUS: STAGE 05 PLACEMENT SUITE COMPLETE - PASS

SECTION 04 — EDA TOOLS

Tools Used in Standard Cell Placement Stage

Modern placement suites employ advanced mathematical solvers to balance wirelength minimization, congestion avoidance, and timing-driven cell clustering.

Task	🏭 Synopsys	🔷 Cadence	🟧 Siemens EDA	🔓 Open-Source
Global Analytical Placement (HPWL)	Synopsys IC Compiler II (ICC2) Place	Cadence Innovus GigaPlace	Siemens Aprisa Place	OpenROAD (RePlAce / ePlace)
Detailed Placement & Legalization	Synopsys ICC2 Legalizer	Cadence Innovus Legalizer	Siemens Aprisa Legalizer	OpenROAD (OpenDP / DPO)
Decap & Filler Cell Insertion	Synopsys ICC2 Filler Gen	Cadence Innovus Decap Manager	Siemens Aprisa Filler Manager	OpenROAD (filler_placement)
Early Congestion Estimation	Synopsys ICC2 Global Router	Cadence Innovus Early Global Route	Siemens Aprisa Congestion Map	OpenROAD (FastRoute Engine)
Post-Placement Timing Closure (STA)	Synopsys PrimeTime (Post-Place)	Cadence Tempus (Post-Place)	Siemens Questa Timing	OpenSTA (estimate_parasitics)