09Tapeout Signoff

Physical Verification (DRC/LVS) & GDSII Tapeout

The final gatekeeper before silicon manufacturing. Physical signoff merges standard cell, SRAM macro, and IO pad GDSII files to execute exhaustive nanometer Design Rule Checks (DRC) and device-level Layout Versus Schematic (LVS) matching. Combined with Multi-Corner Signoff STA and ERC checks, this stage generates the golden GDSII/OASIS stream file sent to the foundry mask shop.

⏱️2–4 weeksTypical Duration

👥Lead Signoff EngineerKey People

📄Tapeout GDSII/OASIS + DRC/LVS CleanDeliverable

🔧Calibre, IC Validator, KLayoutTool Phase

SECTION 01 — STAGE DESCRIPTION

What Happens in Physical Signoff & GDSII Export?

🧩 The Lead Signoff Engineer's Job

During physical design, tools manipulate abstract cell boundaries and simplified wire representations. Physical signoff begins by merging the GDSII layout stream — substituting abstract cell frames with the exact multi-layer polygon geometries of every standard cell, I/O pad, analog block, and SRAM memory compiler macro.

The merged layout undergoes exhaustive Design Rule Checking (DRC) using the foundry's certified rule deck (e.g. Calibre nmDRC or KLayout DRC). The tool checks millions of microscopic geometric rules: minimum metal spacing, poly-silicon gate extension, well enclosure, contact overlap, and metal density window compliance.

Concurrently, Layout Versus Schematic (LVS) extracts the physical transistors, diodes, resistors, and capacitors from the merged diffusion and metal polygons and compares them device-for-device and net-for-net against the golden gate-level SPICE netlist. LVS mathematically proves zero shorts, zero opens, zero missing pins, and zero transistor width/length mismatches. After final multi-corner Signoff STA closure and Electrical Rule Checking (ERC) for substrate noise isolation, the design team executes the formal tapeout signoff review and transmits the finalized GDSII / OASIS stream to the semiconductor fabrication plant.

🏗️

Analogy: Like the final pre-flight inspection and customs clearance before a space mission. Every valve, weld, and sensor circuit is ultrasound-scanned and verified against the engineering blueprint. A single undetected DRC short or LVS discrepancy in silicon creates dead, non-functional wafers — resulting in millions of dollars in lost manufacturing fees and a 6-month product delay.

📋 What Physical Design Provides

Routed DEF with metal fill (picorv32_routed_filled.def)
Foundry standard cell GDSII library (sky130.gds)
Hard macro GDSII layouts (SRAM, PLL, IO pads)
Golden SPICE gate-level netlist (picorv32_golden.sp)
Foundry certified DRC and LVS rule decks
Full-chip multi-corner SPEF parasitics

📐 What the Signoff Team Produces

Golden Tapeout GDSII / OASIS stream file
DRC clean signoff certificate (0 violations)
LVS matching certificate (100% netlist/layout match)
Electrical Rule Checking (ERC) substrate signoff
Multi-Corner Multi-Mode (MCMM) STA timing signoff
Formal tapeout signoff package for foundry fab

SECTION 02 — INPUT / OUTPUT FILES

Files Flow: Stage 09 Inputs & Outputs

📥 INPUTS

picorv32_routed_filled.def

Complete physical placement and routing layout ready for GDS polygon stream merging

From: Stage 07 Routing Suite

sky130_fd_sc_hd.gds

Full physical GDSII polygon definitions for all standard cells, welltaps, and decap cells

From: Stage 01 PDK Foundry

sky130A_drc_lvs.rules

Foundry calibrated geometric DRC and device extraction LVS rule deck

From: Stage 01 PDK Foundry

⚙️ STAGE 09 PROCESS

① GDSII Stream Merging

② Geometric DRC Verification

③ Layout vs Schematic (LVS) Match

④ Electrical Rule Check (ERC)

⑤ Multi-Corner Signoff STA

⑥ Tapeout Signoff & Fab Export

↓

📤 OUTPUT FILES

picorv32_final.gds

Golden Calma GDSII stream binary containing all physical mask layers for photomask fabrication

→ Used by: Foundry Mask Shop

picorv32_final.oas

Open Artwork System Interchange Standard (OASIS) format — 65% smaller file size than GDSII

→ Used by: Modern Photomask Lithography

tapeout_manifest.json

Checksum manifest, layer map table, bounding box coordinates, and die seal ring specs

→ Used by: Foundry Logistics & QA

📊 REPORTS / SIGNOFF

drc_signoff.rpt

Exhaustive Design Rule Check signoff report: 0 DRC violations across all nanometer layers (PASS)

Signoff: Physical Verification Lead

lvs_signoff.rpt

Layout Versus Schematic match certificate: 100% matched devices, 0 shorts, 0 opens (MATCHED)

Signoff: Tapeout Review Board

SECTION 03 — REAL PROJECT WALKTHROUGH

PicoRV32 on SKY130: KLayout DRC & Netgen LVS Tapeout

🔬 OPEN-SOURCE PROJECT

ProjectPicoRV32 Physical Signoff on SkyWater SKY130

Final GDS Size24.8 MB GDSII / 8.2 MB OASIS Stream Binary

DRC EngineKLayout / Magic DRC with sky130A PDK rules

LVS EngineNetgen LVS (100% Netlist-to-Layout Match)

STEP 1

KLayout GDSII Streamout & Merge Python Script (streamout.py)

# KLayout Batch GDSII Stream Merge Script for PicoRV32
import pya

layout = pya.Layout()
layout.read("picorv32_routed_filled.def")

# 1. Merge standard cell and macro GDSII libraries
cell_gds_files = [
    "sky130_fd_sc_hd.gds",
    "sky130_sram_2kb.gds",
    "sky130_fd_io.gds"
]

for gds_file in cell_gds_files:
    sub_layout = pya.Layout()
    sub_layout.read(gds_file)
    layout.copy_tree(sub_layout)

# 2. Write out golden mask stream files
layout.write("picorv32_final.gds")
layout.write("picorv32_final.oas")
print("GDSII & OASIS Stream Merging Complete.")

STEP 2

Magic DRC & Netgen LVS Execution Commands

# 1. Run full geometric DRC with Magic engine
magic -dnull -noconsole << EOF
gds read picorv32_final.gds
load picorv32_top
drc check
drc catchup
drc count
quit
EOF

# 2. Extract SPICE netlist from layout and run Netgen LVS
netgen -batch lvs \
    "picorv32_extracted.sp picorv32_top" \
    "picorv32_golden.sp picorv32_top" \
    sky130A_setup.tcl \
    lvs_signoff.rpt

STEP 3

Physical Verification & Tapeout Certificate (tapeout_signoff.log)

=== PicoRV32 Physical Verification & Tapeout Signoff ===
Design Top : picorv32_top
PDK Node   : SkyWater SKY130 (130nm Commercial Open PDK)
Die Size   : 300.00 µm x 300.00 µm

--- Geometric Design Rule Check (DRC) ---
  Total DRC Rules Evaluated : 482 rules
  Metal 1-5 Spacing / Width : 0 Violations (PASS)
  Via Enclosure / Stacking  : 0 Violations (PASS)
  Diffusion & Well Rules    : 0 Violations (PASS)
  Antenna & Metal Density   : 0 Violations (PASS)
  TOTAL DRC VIOLATIONS      : 0 (100% DRC CLEAN)

--- Layout Versus Schematic (LVS) Verification ---
  Layout Extracted Devices  : 48,240 MOSFETs, 840 Taps
  Schematic Golden Devices  : 48,240 MOSFETs, 840 Taps
  Unmatched Devices         : 0
  Unmatched Nets            : 0
  LVS COMPARISON RESULT     : CIRCUITS ARE FULLY EQUIVALENT (MATCHED)

--- Final Tapeout Deliverables ---
  picorv32_final.gds ....... 24.8 MB (SHA-256 Verified)
  picorv32_final.oas .......  8.2 MB (OASIS Binary)
  Tapeout Checklist ........ APPROVED BY LEAD ARCHITECT
STATUS: STAGE 09 TAPEOUT COMPLETE - READY FOR FOUNDRY FABRICATION

SECTION 04 — EDA TOOLS

Tools Used in Physical Signoff & Tapeout Stage

Physical verification is the ultimate golden signoff step in semiconductor engineering, trusted by foundries worldwide to ensure 100% silicon yield.

Task	🏭 Synopsys	🔷 Cadence	🟧 Siemens EDA	🔓 Open-Source
Design Rule Checking (DRC)	Synopsys IC Validator DRC	Cadence Pegasus DRC	Siemens Calibre nmDRC	KLayout (DRC Engine) · Magic
Layout Versus Schematic (LVS)	Synopsys IC Validator LVS	Cadence Pegasus LVS	Siemens Calibre nmLVS	Netgen · Magic LVS
Electrical Rule Checking (ERC & Latchup)	Synopsys IC Validator ERC	Cadence Pegasus ERC	Siemens Calibre PERC	KLayout ERC Scripts
GDSII / OASIS Stream Merging & MDP	Synopsys CATS / ICV MDP	Cadence Pegasus Mask Prep	Siemens Calibre MDP	KLayout (Python API) · gdsfactory
Golden Signoff Static Timing (STA)	Synopsys PrimeTime	Cadence Tempus	Siemens Questa Timing Signoff	OpenSTA (Full MCMM Mode)