Die Floorplanning, IO/Macros & Power Grid (PDN)
The physical and electrical foundation of the microchip. Physical design engineers establish the silicon die boundary, set target core utilization, position perimeter IO pads and memory macros (SRAM, PLLs) with keep-out halos, insert latch-up prevention welltaps, and synthesize a multi-layer Power Distribution Network (PDN) metal mesh targeting < 15 mV IR-drop.
What Happens in Floorplanning & PDN Synthesis?
🧩 The Physical Design Engineer's Job
Floorplanning transforms the abstract connectivity of the gate-level netlist into a physical geometric blueprint. The engineer defines the die size and core area based on cell area estimates and target utilization (typically 60–75%). Choosing the right aspect ratio and leaving adequate core margins ensures standard cell rows have sufficient routing tracks for later detailed routing.
Next, hard macros (such as embedded SRAM blocks, analog ADCs, and phase-locked loops) and IO pads are placed. Macros are pushed to die edges or corners to create a contiguous central core region, and wide keep-out halos are established around them to prevent standard cells from blocking macro pin access channels. Welltap cells and endcap cells are inserted every 14–20 µm along rows to bias the substrate/N-well and prevent CMOS latch-up.
Finally, the Power Distribution Network (PDN) is synthesized. An orthogonal grid of wide VDD and VSS metal straps is routed on upper low-resistance metal layers (Met4/Met5 in SKY130), forming rings around macros and dropping via stacks to standard cell power rails (Met1). Static IR-drop analysis verifies that supply voltage never drops by more than 1.5% across any transistor under full load.
📋 What Synthesis & PDK Provide
- Scan-inserted gate-level netlist (synthesis_scan.v)
- Technology LEF (metal layers, pitches & design rules)
- Standard cell physical LEF models (cell dimensions)
- Hard macro LEF models (SRAM, PLL pin layouts)
- Target die dimensions & package pinout map
- Max allowable IR-drop limit (e.g. < 15 mV)
📐 What the Floorplan Engineer Produces
- Complete floorplan DEF (die area & row definitions)
- PDN metal strap mesh & power ring DEF
- Legalized IO pin & pad perimeter locations
- Hard macro placement with keep-out halos
- Substrate tap & endcap cell insertion grid
- Static IR-drop & power grid resistance signoff report
Files Flow: Stage 04 Inputs & Outputs
PicoRV32 on SKY130: OpenROAD Floorplan & PDN Mesh
OpenROAD Floorplan Initialization TCL Script (floorplan.tcl)
# OpenROAD Floorplan Execution Script for PicoRV32 on SKY130
read_lef sky130_fd_sc_hd.tlef
read_lef sky130_fd_sc_hd.lef
read_lef sky130_sram_2kb.lef
read_verilog picorv32_scan.v
link_design picorv32_top
# 1. Initialize Floorplan: 300um x 300um Die, 20um Core Margins
initialize_floorplan \
-die_area "0 0 300.0 300.0" \
-core_area "20.0 20.0 280.0 280.0" \
-site unithd
# 2. Place IO Pins equidistant along metal 2 / metal 3 layers
place_pins -hor_layers met3 -ver_layers met2 -random_seed 42
# 3. Insert Tapcells every 14um to prevent CMOS Latch-up
tapcell \
-endcap_cpp 2 \
-distance 14 \
-tapcell_master "sky130_fd_sc_hd__tapvpwrvgnd_1" \
-endcap_master "sky130_fd_sc_hd__decap_4"OpenROAD PDN Mesh Configuration (pdn.cfg / tcl)
# Power Distribution Network (PDN) Synthesis Script
add_global_connection -net VDD -pin_pattern "^VPWR$" -power
add_global_connection -net VSS -pin_pattern "^VGND$" -ground
# 1. Standard Cell Rails on Metal 1
add_pdn_stripe -grid stdcell -layer met1 -width 0.48 -followpins
# 2. Met4 Vertical Straps (Supply Mesh)
add_pdn_stripe -grid stdcell \
-layer met4 \
-width 1.60 \
-pitch 40.0 \
-offset 2.0 \
-nets {VDD VSS}
# 3. Met5 Horizontal Straps (Upper Low-Resistance Mesh)
add_pdn_stripe -grid stdcell \
-layer met5 \
-width 1.60 \
-pitch 40.0 \
-offset 2.0 \
-nets {VDD VSS}
# 4. Connect via stacks across all overlapping metal layers
add_pdn_connect -grid stdcell -layers {met1 met4}
add_pdn_connect -grid stdcell -layers {met4 met5}
pdngenFloorplan & Static IR-Drop Signoff Report (floorplan_signoff.rpt)
=== OpenROAD Floorplan & PDN Signoff: PicoRV32 ===
Design Top : picorv32_top
Technology : SkyWater SKY130 HD (130nm)
--- Die Area & Utilization ---
Total Die Area : 90,000.00 µm² (300.00 µm x 300.00 µm)
Total Core Area : 67,600.00 µm² (260.00 µm x 260.00 µm)
Standard Cell Area : 46,240.00 µm²
Core Utilization : 68.4% (Target 65-72% PASS)
--- Physical Elements Placed ---
IO Pins Assigned : 128 pins (Met2/Met3 tracks legalized)
SRAM Hard Macros : 1 Block (Placed at bottom-left, 5µm halo clean)
Welltap Cells Added : 840 instances (100% pitch compliance)
Endcap Cells Added : 196 instances (Row diffusion terminated)
--- Static IR-Drop Analysis (PSM Engine) ---
Nominal Supply (VDD) : 1.800 V
Worst Voltage Drop : 0.0082 V (8.2 mV max drop)
Worst Cell Node : 1.7918 V (99.54% nominal voltage)
Target Drop Limit : < 15.0 mV (PASS)
STATUS: STAGE 04 FLOORPLAN SUITE COMPLETE - PASSTools Used in Floorplanning & PDN Stage
Floorplanning and power grid generation require tightly integrated geometric engines that couple physical layout with electrical IR-drop estimation.
| Task | 🏭 Synopsys | 🔷 Cadence | 🟧 Siemens EDA | 🔓 Open-Source |
|---|---|---|---|---|
| Die Sizing & Core Boundary Floorplanning | Synopsys IC Compiler II (ICC2) | Cadence Innovus Floorplan | Siemens Aprisa Floorplan | OpenROAD (initialize_floorplan) |
| IO Pad Ring & Pin Track Assignment | Synopsys ICC2 Pin Planner | Cadence Innovus Pin Editor | Siemens Aprisa Pin Editor | OpenROAD (place_pins / io_placer) |
| Power Grid (PDN) Metal Mesh Synthesis | Synopsys ICC2 PG Mesh | Cadence Innovus Power Plan | Siemens Aprisa PowerMesh | OpenROAD (pdngen) |
| Macro Placement & Keep-Out Halo Routing | Synopsys Fusion Compiler Macro | Cadence Innovus Macro Placer | Siemens Aprisa MacroPlacer | OpenROAD (manual / autoplacer) |
| Static IR-Drop & Power Grid Analysis | Synopsys PrimePower / RedHawk | Cadence Voltus-FI | Siemens mPower Digital | OpenROAD (PSM - Power Source Mgr) |