06Clock Network

Clock Tree Synthesis & Skew Balancing

The clock signal is the heartbeat of every synchronous microchip. Clock Tree Synthesis (CTS) constructs an optimized, symmetrical buffer distribution network (CLKBUF/CLKINV) to deliver the clock edge from the source oscillator to thousands of sequential flip-flops simultaneously — minimizing clock skew (< 35 ps), controlling insertion latency, and closing hold timing margins.

⏱️1–3 weeksTypical Duration

👥CTS & Timing SpecialistKey People

📄CTS DEF + SDC Latency + Post-CTS STADeliverable

🔧TritonCTS, CCOpt, OpenSTATool Phase

SECTION 01 — STAGE DESCRIPTION

What Happens in Clock Tree Synthesis?

🧩 The CTS & Timing Specialist's Job

During RTL design and placement, EDA tools assume an ideal clock that arrives everywhere instantaneously at t = 0. In real silicon, clock wires have distributed resistance and capacitance, and driving 4,000+ flip-flops from a single clock pin would cause catastrophic signal degradation, massive transition slews, and severe clock skew. CTS builds the physical buffer network that makes high-frequency synchronous execution possible.

Algorithms (such as TritonCTS or CCOpt) analyze the spatial distribution of all flip-flop clock pins (sinks) and build a hierarchical H-tree or clustering buffer network. Dedicated, symmetrical clock buffers (CLKBUF) and inverters (CLKINV) are inserted at branching points to balance capacitive loads and maintain clock slews under 0.20 ns. Clock routes are assigned to upper thick metal layers (Met4/Met5) with double-width spacing rules to eliminate capacitive crosstalk from switching data nets.

CTS also leverages Useful Skew — intentionally delaying the clock to a launching register on a timing-critical path to give downstream logic additional setup slack. Finally, Post-CTS Static Timing Analysis is executed with propagated real clock latencies, fixing any newly revealed hold-time violations by inserting delay buffers on short data paths.

🏗️

Analogy: Like an orchestra conductor whose baton beat must reach 100 musicians at the exact same microsecond, or an industrial water irrigation manifold where pipes branch symmetrically with equal lengths and diameters so every sprinkler head receives identical pressure at the exact same instant.

📋 What Placement Provides

Filled placement DEF (exact flip-flop locations)
SDC clock constraints (period, jitter, uncertainty)
Foundry clock cell Liberty library (.lib)
Integrated Clock Gating (ICG) cell positions
Max allowable skew budget (e.g. < 40 ps)
Clock transition slew targets (< 0.20 ns)

📐 What the CTS Specialist Produces

CTS DEF with placed & routed clock buffer tree
Clock tree skew & insertion latency report
Updated SDC with propagated clock latencies
Hold-violation fix report (delay buffer insertions)
Clock tree dynamic power consumption report
Post-CTS STA timing signoff (Setup & Hold met)

SECTION 02 — INTERACTIVE CLOCK BALANCING LABORATORY

Visualizing Clock Tree Topologies & Skew Physics

Compare real-time wavefront propagation, latency variance, and hold-time race hazards across Unbalanced Daisy-Chains, Symmetrical H-Trees, TritonCTS Clustered Buffer Trees, and High-Performance Clock Meshes.

⏱️INTERACTIVE CLOCK ARCHITECTURE & SKEW SIMULATOR

Clock Tree Topologies & Real-Time Skew Balancer

Switch between clock distribution architectures to see how symmetrical routing, buffer sizing, and clustering prevent catastrophic clock skew and eliminate hold-time race conditions.

⏱️ TIMING DIAGRAM: LAUNCH vs. CAPTURE SKEW IMPACT Launch Clk (Earliest Sink) Capture Clk (Latest Sink) Skew (ΔT)

📊 REAL-TIME CLOCK TREE QoR HUDCRITICAL SKEW HAZARD

MAX INSERTION DELAY (T_max)720.0 psSink: FF_06 [UART]

MIN INSERTION DELAY (T_min)50.0 psSink: FF_01 [ALU]

GLOBAL CLOCK SKEW (ΔT)670.0 psTarget: < 35.0 ps

CLOCK BUFFER COUNT0 CellsCLKBUF / CLKINV

⚠️TIMING CLOSURE & RACE HAZARD ANALYSIS

🚨 CATASTROPHIC HOLD VIOLATION HAZARD: With a 670 ps clock skew on fast combinational paths (T_clk-q + T_comb < T_skew + T_hold), the launching data overwrites the receiving flip-flop in the same clock cycle before the prior data is captured!

Setup Margin (Max Path):-0.45 ns (FAIL)

Hold Margin (Min Path):-0.62 ns (FATAL)

Clock Tree Power:3.2 mW

🎛️ PHYSICAL PARAMETER TUNER

Clock Frequency (Period):50 MHz (20.0 ns)

Metal Layer RC Quality:Met3 Standard (1.0x RC)

On-Chip Variation (OCV / Jitter Derate):5% (Typical PVT)

💡 Silicon CTS Physics & Best Practices

Why Inverters (`CLKINV`) instead of Buffers? Clock buffers consist of two back-to-back inverters. Because PMOS pull-up is naturally slower than NMOS pull-down, successive buffer stages accumulate rise/fall duty-cycle distortion. Alternating inverters along the tree cancels out asymmetry and minimizes skew.
Why Positive Skew Hurts Hold Time: When capture clock arrival (T_clk2) is delayed relative to launch clock (T_clk1), the required hold time increases directly by ΔT_skew. On short logic paths, new data arrives before the old data is locked, causing unfixable silicon failures.
Upper Metal Shielding (Met4/Met5): Clock nets switch continuously at high frequency. Placing them on thick upper metal layers with adjacent VDD/VSS shielding wires suppresses crosstalk glitch coupling into sensitive neighbor data nets.

📐 Mathematical Clock Skew Definition

For any two synchronously communicating flip-flops (Launch Register FF₁ and Capture Register FF₂), clock skew is the difference in arrival times from the clock root:

T_skew = T_latency(Capture Clk) - T_latency(Launch Clk)

• Positive Skew (T_capture > T_launch): Clock arrives at capture flop later. Adds extra time for logic (T_setup margin increases), but worsens hold time margin.
• Negative Skew (T_capture < T_launch): Clock arrives at capture flop earlier. Reduces available setup time, but relieves hold time.

💥 Why Skew Causes Hold Violations on Fast Paths

Hold time requires data to remain stable at the capture flip-flop for T_hold after the active clock edge. The hold margin is given by:

Slack_hold = (T_clk_to_q + T_comb_min) - (T_skew + T_hold + T_unc)

⚠️ If T_skew is positive and large (e.g. +670 ps in unbuffered trees), a fast buffer or wire (T_comb ≈ 50 ps) causes Hold Slack < 0. The newly launched data clobbers the previous cycle's data before it can be latched!

SECTION 03 — INPUT / OUTPUT FILES

Files Flow: Stage 06 Inputs & Outputs

📥 INPUTS

picorv32_filled.def

Fully placed and legalized DEF with Decap and filler cells from Stage 05

From: Stage 05 Placement Suite

constraints.sdc

Clock period (20.0 ns / 50 MHz), max latency, and clock uncertainty margins

From: Stage 01 System Spec

sky130_fd_sc_hd__clk.lib

Characterized delay models for clock buffers (CLKBUF_4, CLKBUF_8, CLKINV_1)

From: Stage 01 PDK Library

⚙️ STAGE 06 PROCESS

① Clock Sink Clustering & Sizing

② Hierarchical Buffer Tree Insertion

③ Shielded Upper-Metal Clock Routing

④ Skew & Insertion Latency Balancing

⑤ Useful Skew Delay Optimization

⑥ Post-CTS Hold/Setup STA Signoff

↓

📤 OUTPUT FILES

picorv32_cts.def

DEF with 342 inserted clock buffer cells and preliminary upper-metal clock interconnects

→ Used by: Stage 07 Routing Suite

post_cts_constraints.sdc

SDC file updated with set_propagated_clock and real insertion delays for downstream tools

→ Used by: Routing & Signoff STA

clock_tree_topology.rpt

Detailed hierarchical tree breakdown: buffer levels, fanout per stage, and load capacitances

→ Used by: Clock Architecture Review

📊 REPORTS / SIGNOFF

cts_skew_latency.rpt

Clock skew report: Max Skew = 28.4 ps (< 40 ps PASS), Source-to-Sink Latency = 412 ps

Signoff: CTS Timing Lead

post_cts_sta_signoff.rpt

Timing closure report with real clock latency: Setup WNS = +2.08 ns, Hold WHR = +0.18 ns (PASS)

Signoff: Timing Signoff Lead

SECTION 04 — REAL PROJECT WALKTHROUGH

PicoRV32 on SKY130: TritonCTS Clock Tree Synthesis

🔬 OPEN-SOURCE PROJECT

ProjectPicoRV32 Clock Tree Synthesis on SKY130

Clock Sinks4,120 Scan Flip-Flop Clock Pins

Max Skew28.4 ps (Target < 40.0 ps met with 11.6 ps margin)

Clock Buffers312 CLKBUF + 30 CLKINV (342 total cells)

STEP 1

OpenROAD TritonCTS Execution Script (cts.tcl)

# TritonCTS Clock Tree Synthesis for PicoRV32 on SKY130
read_def picorv32_filled.def
read_sdc picorv32_constraints.sdc

# 1. Set Clock Wire RC Models (Upper Metals Met4/Met5 for low resistance)
set_wire_rc -clock -layer met4

# 2. Configure TritonCTS Buffer Whitelist and Sink Clustering
set_cts_sink_clustering_size 32
set_cts_sink_clustering_max_diameter 50

clock_tree_synthesis \
    -root_buf "sky130_fd_sc_hd__clkbuf_16" \
    -buf_list "sky130_fd_sc_hd__clkbuf_8 sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_2" \
    -sink_clustering \
    -distance_between_buffers 100

STEP 2

Hold Timing Repair & Propagated Clock SDC Annotation

# 1. Propagate real clock latencies across all sequential registers
set_propagated_clock [all_clocks]

# 2. Repair Hold Time Violations by inserting delay buffers on short data paths
repair_hold_violations \
    -buffer_cell "sky130_fd_sc_hd__clkbuf_1" \
    -max_buffer_percent 10

# 3. Re-estimate parasitics and export post-CTS DEF
estimate_parasitics -placement
write_def picorv32_cts.def
write_sdc post_cts_constraints.sdc

STEP 3

CTS Skew & Post-CTS Timing Signoff Report (cts_signoff.rpt)

=== TritonCTS Clock Tree Synthesis Signoff: PicoRV32 ===
Clock Net      : clk (50.0 MHz / Period = 20.00 ns)
Target Library : sky130_fd_sc_hd (SkyWater 130nm)

--- Clock Tree Topology & Skew Summary ---
  Total Clock Sinks Driven  : 4,120 flip-flops
  Total Clock Buffer Cells  :   312 instances (CLKBUF_4 / CLKBUF_8)
  Total Clock Inverters     :    30 instances (CLKINV_1)
  Clock Tree Levels         : 4 levels (H-Tree hierarchy)
  Total Clock Wire Length   : 0.42 meters
  Earliest Clock Arrival    : 0.384 ns (Sink: u_core/reg_pc[2])
  Latest Clock Arrival      : 0.412 ns (Sink: u_uart/tx_shift[7])
  MAX CLOCK SKEW            : 0.0284 ns (28.4 ps PASS / Target < 40 ps)

--- Post-CTS STA Timing Results (Propagated Clock) ---
  Setup Worst Negative Slack (WNS) : +2.08 ns  (SS Corner / 100°C)
  Setup Total Negative Slack (TNS) :  0.00 ns
  Hold Worst Hold Slack (WHR)      : +0.18 ns  (FF Corner / -40°C)
  Hold Violations Count            : 0 violations (PASS)
STATUS: STAGE 06 CLOCK TREE SYNTHESIS COMPLETE - PASS

SECTION 05 — EDA TOOLS

Tools Used in Clock Tree Synthesis Stage

Clock tree synthesis engines solve complex RC delay balancing equations to achieve sub-40 picosecond skew while managing clock power dissipation.

Task	🏭 Synopsys	🔷 Cadence	🟧 Siemens EDA	🔓 Open-Source
Clock Tree Synthesis & Buffer Insertion	Synopsys IC Compiler II (ICC2) CCOpt	Cadence Innovus CCOpt-CTS	Siemens Aprisa Clock	OpenROAD (TritonCTS)
Clock Skew Balancing & Latency Control	Synopsys ICC2 Skew Balancer	Cadence Innovus Skew Optimizer	Siemens Aprisa Skew Engine	OpenROAD (CTS Balance)
Hold Violation Delay Buffer Insertion	Synopsys ICC2 Hold Fixer	Cadence Innovus OptDesign -hold	Siemens Aprisa Hold Repair	OpenROAD (repair_hold_violations)
Useful Skew Scheduling & Optimization	Synopsys Fusion Compiler Useful Skew	Cadence Innovus Useful Skew	Siemens Aprisa Useful Skew	OpenROAD (repair_clock_nets)
Propagated Clock Static Timing Analysis	Synopsys PrimeTime (Post-CTS)	Cadence Tempus (Post-CTS)	Siemens Questa Timing	OpenSTA (set_propagated_clock)