08Parasitic & Power Signoff

Parasitic RC Extraction & Dynamic IR-Drop/EM

Extracting true physical parasitics from routed metal geometries and stress-testing the power grid. Field-solver RC extractors output Standard Parasitic Exchange Format (SPEF) files across process corners (RC-Max, RC-Min, C-Max), enabling signoff timing closure, while vector-based dynamic IR-drop and electromigration (EM) simulations prove power rail integrity under peak switching workloads.

⏱️1–3 weeksTypical Duration

👥Signoff & Power SpecialistKey People

📄Multi-Corner SPEF + Dynamic IR/EM SignoffDeliverable

🔧OpenRCX, Voltus, RedHawkTool Phase

SECTION 01 — STAGE DESCRIPTION

What Happens in Parasitic Extraction & Power Integrity?

🧩 The Signoff & Power Specialist's Job

After detailed routing, wires are physical copper/aluminum conductors possessing finite resistance and strong capacitive coupling to adjacent wires and the silicon substrate. The parasitic extraction engine uses 2.5D/3D field solvers and calibrated foundry technology files to calculate every wire segment's resistance (R), ground capacitance (C_g), and cross-coupling capacitance (C_c), generating standardized SPEF (Standard Parasitic Exchange Format) files across multiple process corners (Nominal, RC-Max, RC-Min).

Crosstalk analysis uses extracted C_c models to calculate delay push-out/pull-in caused by neighboring aggressor nets switching simultaneously. Back-annotating SPEF into Static Timing Analysis gives the true, tapeout-grade timing slack of the chip.

Concurrently, Dynamic IR-Drop and Electromigration (EM) analysis stress-tests the Power Distribution Network (PDN). By reading cycle-accurate switching vectors (VCD/FSDB from logic simulation), the power engine simulates transient current spikes (I(t)) as thousands of flip-flops switch simultaneously on a clock edge. Peak dynamic voltage drops are verified to stay below 1.5–2.0% of nominal VDD (< 25 mV) to prevent setup time failures, while current densities through metal lines and vias are verified against foundry electromigration limits to prevent physical wire breakdown over the chip's 10-year lifetime.

🏗️

Analogy: Like stress-testing a suspension bridge under bumper-to-bumper rush hour traffic during a storm. Static calculations ensure the bridge holds stationary weight, but dynamic simulation tests whether thousands of heavy vehicles braking at the exact same instant create dangerous resonant oscillations or voltage brownouts that trip the bridge's safety lighting.

📋 What Routing Provides

Routed DEF with dummy metal fill (picorv32_routed.def)
Foundry RC extraction rule deck (sky130.rcx.rules)
Cycle-accurate simulation activity file (firmware.vcd)
Propagated SDC timing constraints
Multi-corner Liberty timing libraries (.lib)
Target dynamic IR-drop limit (e.g. < 25 mV)

📐 What the Power Specialist Produces

Extracted SPEF parasitics across PVT corners
Back-annotated STA timing signoff with crosstalk
Dynamic IR-drop 2D voltage heatmap & report
Electromigration (EM) current density signoff report
Full-chip power dissipation breakdown (Active & Leakage)
Battery life / energy budget validation report

SECTION 02 — INPUT / OUTPUT FILES

Files Flow: Stage 08 Inputs & Outputs

📥 INPUTS

picorv32_routed.def

Completed physical layout containing all routed metal tracks, contact vias, and dummy metal fill

From: Stage 07 Routing Suite

sky130.rcx.rules

Foundry calibrated 3D field-solver extraction technology file defining dielectric constants and layer resistivities

From: Stage 01 PDK Foundry

activity_vectors.vcd

Value Change Dump file recording toggle rates and switching events from embedded firmware execution

From: Stage 02 Logic Verification

⚙️ STAGE 08 PROCESS

① 2.5D/3D RC Parasitic Extraction

② Multi-Corner SPEF Generation

③ Back-Annotated STA & Crosstalk Check

④ VCD Activity Toggle Annotation

⑤ Vector-Based Dynamic IR-Drop

⑥ Electromigration (EM) Sign-off

↓

📤 OUTPUT FILES

picorv32_nominal.spef

IEEE Standard Parasitic Exchange Format containing node-by-node RC networks at TT corner

→ Used by: Signoff STA & Power Tools

picorv32_rcmax.spef

Worst-case RC extraction corner (high metal resistance, max coupling cap) for setup timing

→ Used by: Multi-Corner Signoff STA

dynamic_ir_map.png

Full-die 2D color contour heatmap showing power grid voltage drop during peak switching cycles

→ Used by: Power Integrity Review

📊 REPORTS / SIGNOFF

dynamic_ir_drop.rpt

Peak dynamic IR-drop report: Worst Drop = 14.2 mV (< 25.0 mV Limit PASS)

Signoff: Power Integrity Lead

em_signoff_summary.rpt

Electromigration current density report: 0 wire violations, 0 via over-current warnings (PASS)

Signoff: Reliability Lead

SECTION 03 — REAL PROJECT WALKTHROUGH

PicoRV32 on SKY130: OpenRCX & Dynamic IR Signoff

🔬 OPEN-SOURCE PROJECT

ProjectPicoRV32 Parasitic & Power Signoff on SKY130

Total Cap14.20 pF total extracted interconnect capacitance

Peak Dynamic IR14.2 mV max drop (< 25 mV limit met with 10.8 mV margin)

Active Power4.82 mW @ 50 MHz (Within customer < 5.0 mW budget)

STEP 1

OpenRCX Parasitic Extraction TCL Script (extract.tcl)

# OpenRCX Parasitic Extraction for PicoRV32 on SKY130
read_lef sky130_fd_sc_hd.tlef
read_lef sky130_fd_sc_hd.lef
read_def picorv32_routed_filled.def

# 1. Configure OpenRCX with SkyWater 130nm calibrated models
define_process_corner -ext_model_file sky130_fd_sc_hd.rcx.rules

# 2. Extract parasitic resistances and ground/coupling capacitances
extract_parasitics \
    -ext_model_file sky130_fd_sc_hd.rcx.rules \
    -max_res 50 \
    -coupling_threshold 0.1

# 3. Export IEEE Standard Parasitic Exchange Format (SPEF)
write_spef picorv32_nominal.spef

STEP 2

Vector-Based Power & Dynamic IR Analysis Script

# OpenSTA / PSM Power and Dynamic IR-Drop Simulation
read_spef picorv32_nominal.spef
read_sdc post_cts_constraints.sdc

# 1. Annotate switching activity from simulation VCD
read_vcd -scope "picorv32_tb/u_dut" firmware_activity.vcd

# 2. Run full-chip dynamic power calculation
report_power -outfile power_summary.rpt

# 3. Simulate transient dynamic IR-drop on power grid (PSM engine)
check_power_grid -net VDD -vcd firmware_activity.vcd -outfile dynamic_ir.rpt

STEP 3

Dynamic IR & Power Signoff Report (power_signoff.rpt)

=== Parasitic RC & Power Integrity Signoff: PicoRV32 ===
Design Top : picorv32_top
Supply VDD : 1.800 V @ 50.0 MHz

--- Extracted Parasitic Statistics ---
  Total Net Count              : 14,820 nets
  Total Wire Resistance (R)    : 412.5 kΩ
  Total Ground Capacitance (Cg):  9.84 pF
  Total Coupling Cap (Cc)      :  4.36 pF
  Total Extracted Capacitance  : 14.20 pF

--- Full-Chip Power Dissipation Breakdown ---
  Internal Gate Power          : 2.14 mW (44.4%)
  Interconnect Switching Power : 2.42 mW (50.2%)
  Leakage Power                : 0.26 mW  (5.4%)
  TOTAL ACTIVE POWER           : 4.82 mW (< 5.0 mW Budget PASS)

--- Dynamic IR-Drop & Electromigration (EM) Signoff ---
  Peak Dynamic IR-Drop         : 0.0142 V (14.2 mV Worst Drop)
  Max Allowable Drop Target    : 0.0250 V (25.0 mV Target PASS)
  Electromigration (EM) Status : 0 Wire Violations / 0 Via Violations (PASS)
STATUS: STAGE 08 PARASITIC & POWER INTEGRITY COMPLETE - PASS

SECTION 04 — EDA TOOLS

Tools Used in Parasitic & Power Signoff Stage

Parasitic extraction and power integrity tools employ 3D electromagnetic field solvers and transient SPICE-like numerical engines to model nanometer wire physics.

Task	🏭 Synopsys	🔷 Cadence	🟧 Siemens EDA	🔓 Open-Source
3D Field RC Parasitic Extraction (SPEF)	Synopsys StarRC	Cadence Quantus QRC	Siemens Calibre xRC / xACT	OpenRCX · FasterCap
Dynamic Vector-Based IR-Drop Simulation	Synopsys PrimePower / RedHawk	Cadence Voltus Power Integrity	Siemens mPower Digital	OpenROAD (PSM Engine)
Electromigration (EM) Current Verification	Synopsys PrimePower EM	Cadence Voltus EM	Siemens mPower EM	OpenROAD (EM Analyzer)
Full-Chip Dynamic & Leakage Power	Synopsys PrimePower	Cadence Joules / Voltus	Siemens PowerPro	OpenSTA (report_power)
Signal Integrity & Crosstalk Delay	Synopsys PrimeTime SI	Cadence Tempus SI	Siemens Questa Timing SI	OpenSTA (Crosstalk Engine)