VLSI Design Flow

VLSI (Very Large Scale Integration) design flow is the structured, step-by-step engineering methodology of designing and fabricating complex Integrated Circuits (ICs) containing millions to billions of transistors on a single silicon substrate. It encompasses the entire lifecycle from architectural specification, RTL coding, and functional verification, to logic synthesis, physical design (floorplanning, placement, CTS, routing), timing signoff (STA), and physical verification (DRC/LVS) to produce tapeout-ready GDSII mask data for semiconductor foundries.

The standard VLSI design flow consists of sequential front-end and back-end stages:

1. System Specifications: Architecture definition, timing constraints (SDC), and power intent (UPF).
2. RTL Design & Verification: Behavioral HDL coding in Verilog/SystemVerilog and testbench simulation.
3. Logic Synthesis: Translating RTL into a gate-level netlist targeting standard cell liberty (.lib) files.
4. Design For Test (DFT): Scan chain insertion and ATPG test vector generation.
5. Logic Equivalence Checking (LEC): Proving formal equivalence between RTL and synthesized netlist.
6. Floorplanning & Power Planning: Die sizing, IO pad allocation, macro placement, and VDD/VSS PDN mesh.
7. Standard Cell Placement: Global placement, wirelength minimization, and row legalization.
8. Clock Tree Synthesis (CTS): Constructing balanced clock buffer networks to eliminate clock skew.
9. Routing: Global routing and detailed multi-layer metal interconnect assignment.
10. Parasitic Extraction (SPEF): 3D field-solver RC extraction.
11. Static Timing Analysis (STA): Setup and hold timing closure across multi-corner PVT variations.
12. Physical Verification: DRC, LVS, ERC, and antenna rule signoff before GDSII export.

The complete VLSI design flow from RTL to GDS bridges abstract software-like hardware descriptions with physical foundry manufacturing masks. It begins with logic synthesis (Yosys, Synopsys Design Compiler) mapping RTL to gate primitives. Next, physical design establishes the floorplan envelope, synthesizes the power distribution network (PDN), places standard cells, builds symmetrical clock trees (CTS), and routes multi-level metal interconnects. Finally, extracted SPEF parasitics enable multi-corner Static Timing Analysis (STA) and DRC/LVS physical verification, yielding clean GDSII/OASIS files ready for silicon fabrication.

The RTL to GDS flow (often abbreviated as RTL2GDS2) is the automated EDA implementation pipeline that transforms digital hardware described at the Register-Transfer-Level (in Verilog, VHDL, or SystemVerilog) into the final GDSII stream format containing the precise 2D/3D polygon coordinates needed for lithographic mask manufacturing.

The core execution steps in the RTL to GDS flow include:

• 1. Synthesis: Converts behavioral RTL code into technology-mapped gate netlists.
• 2. Floorplanning: Sets core aspect ratio, die boundary dimensions, and places SRAM memory macros.
• 3. Power Planning (PDN): Generates low-impedance VDD/VSS power rings and metal straps.
• 4. Placement: Places standard logic gates and legalizes cell locations to optimize wirelength.
• 5. Clock Tree Synthesis (CTS): Builds balanced clock buffer trees and optimizes skew with cts_opt.
• 6. Routing: Performs global and detailed routing across all signal pins and metal layers.
• 7. RC Extraction & STA: Extracts wire parasitics into SPEF to verify setup and hold slack margins.
• 8. Physical Verification: Runs DRC (Design Rule Checks) and LVS (Layout vs. Schematic) before exporting GDSII.

ASIC (Application-Specific Integrated Circuit) design flow is a dedicated semiconductor design methodology tailored for a customized silicon chip (such as an AI accelerator, GPU, or 5G baseband processor). Unlike programmable FPGAs, an ASIC goes through an irreversible, rigorous physical design and foundry manufacturing process optimized for peak clock frequency, minimal silicon area, ultra-low power dissipation, and high-volume unit manufacturing economics.

The primary differences between RTL and GDS are:

• RTL (Register-Transfer-Level): A human-readable, behavioral hardware description (written in Verilog, SystemVerilog, or VHDL) describing logical operations and data transfers between clock-driven registers. It contains no physical dimensions, coordinate positions, or metal layer data.
• GDS (GDSII / OASIS): A machine-readable, binary hierarchical database representing physical silicon layout geometries. It defines exact 2D/3D polygons, planar coordinates, and process mask layer numbers used directly by foundry photolithography machines to fabricate ICs.

After RTL design is finalized, the chip undergoes:

1. RTL Linting & Coding Style Checks: Detects unclocked latches, syntax errors, and undriven signals.
2. Functional Verification: Executes comprehensive testbench simulations and assertions (SystemVerilog/UVM) to achieve 100% functional and code coverage.
3. CDC & UPF Intent Checks: Validates Clock Domain Crossing synchronizers and power domain definitions.
4. Logic Synthesis: Compiles the golden RTL into a technology-mapped gate netlist under SDC timing constraints.

After logic synthesis generates a gate-level netlist:

1. Logic Equivalence Checking (LEC): Formally proves mathematical equivalence between RTL and the gate netlist.
2. Design For Test (DFT) Insertion: Inserts scan chains and generates ATPG vectors for post-silicon testing.
3. Post-Synthesis STA: Verifies baseline timing paths under ideal clock assumptions.
4. Physical Design Handover: Transfers the netlist, SDC constraints, and LEF/DEF library files to physical design tools for floorplanning.

The complete steps in physical design (Back-End design) are:

1. Design Import (Gate Netlist, LEF/DEF, Liberty .lib, SDC)
2. Die Floorplanning & IO Pad Ring Allocation
3. Macro Placement & Halo Keep-Out Definition
4. Power Planning (PDN Rings & Straps)
5. Standard Cell Global & Detail Placement
6. Decap & Filler Cell Insertion
7. Clock Tree Synthesis (CTS) & cts_opt
8. Global & Detailed Metal Routing
9. Antenna Diode Protection & Metal Fill Insertion
10. Parasitic RC Extraction (SPEF)
11. Signoff Static Timing Analysis (STA Closure)
12. Physical Verification (DRC, LVS, ERC, DFM)
13. GDSII / OASIS Mask Streaming

Physical design in VLSI is the back-end engineering discipline that transforms a gate-level netlist into a manufacturable silicon layout. It places millions or billions of standard logic cells within a defined die boundary, builds low-impedance power distribution networks, balances clock trees, and routes microscopic metal tracks across multi-layer stacks while strictly honoring foundry design rules (DRC), timing constraints (STA), and electrical signal integrity limits.

The physical design flow is the ordered sequence of back-end EDA stages: Floorplan → Powerplan (PDN) → Placement → Clock Tree Synthesis (CTS) → cts_opt → Routing → Parasitic Extraction (SPEF) → STA Timing Closure → DRC/LVS Signoff → GDSII Export.

Floorplanning is the foundational phase of physical design where the physical boundary and core dimensions of the silicon chip are established. Engineers define the die aspect ratio, target core utilization (typically 50%–70%), position primary IO pads, place hardened memory macros (SRAMs/ROMs) and analog blocks along the core periphery to prevent routing bottlenecks, and allocate macro halos to isolate high-density standard cell rows.

Placement in VLSI is the stage where standard logic gates (such as NAND, NOR, multiplexers, and flip-flops) are assigned exact coordinates inside core site rows. Placement operates in two passes: Global Placement (which optimizes Half-Perimeter Wire Length and distributes cell density across the die to eliminate routing hotspots) and Detail Placement / Legalization (which aligns cells to discrete site rows without overlap and aligns power/ground rails).

Clock Tree Synthesis (CTS) is the physical design step that creates an optimized distribution network using dedicated clock buffers (CLKBUF) and inverters (CLKINV) to deliver clock pulses from a clock generator/PLL to all sequential registers across the chip with minimal insertion delay and balanced arrival times.

In physical design, CTS stands for Clock Tree Synthesis. It replaces idealized zero-delay clock assumptions with a physical clock tree architecture (such as an H-Tree, Clustered Buffer Tree, or Clock Mesh). CTS balances path latencies across all register clock pins to minimize clock skew (< 35 ps), control clock jitter, and prevent fatal hold-time race conditions.

Routing is the physical design process of creating physical metal traces and inter-layer contact vias to electrically interconnect all placed standard cell pins, macro terminals, and IO pads according to the logical netlist. It is divided into Global Routing (which partitions the chip into routing tiles and determines optimal path assignments) and Detailed Routing (which generates exact manufacturing-grid metal geometries from Met1 through top metals honoring design rules).

Timing closure is the iterative engineering process of optimizing a digital circuit until all timing paths satisfy both Setup Slack (≥ 0.00 ps, maximum path delay) and Hold Slack (≥ 0.00 ps, minimum path delay) across all operating PVT corners and functional modes. Techniques include gate sizing, multi-threshold voltage swapping (HVT → LVT), buffer insertion, wire widening, and useful skew scheduling.

Signoff in VLSI is the formal qualification gate where a completed physical design undergoes golden analysis tools to verify it is 100% tapeout-ready for foundry fabrication. Key signoff checks include:

• STA Signoff: Zero setup (WNS/TNS) and zero hold violations across multi-corner multi-mode (MCMM) PVT libraries with OCV/POCV derates.
• Physical Verification Signoff: Zero DRC (Design Rule Checks) and zero LVS (Layout vs. Schematic) discrepancies.
• Power & Reliability Signoff: Static/dynamic IR-drop below threshold (≤ 5% VDD), zero electromigration (EM) violations, and complete antenna diode coverage.

After standard cell placement is legalized, the physical design flow proceeds through:

1. High-Fanout Net Synthesis (HFNS) & Decap Insertion: Buffers high-fanout resets/enables and adds decoupling capacitors.
2. Clock Tree Synthesis (CTS): Builds balanced clock buffer trees to distribute clock signals.
3. Post-CTS Optimization (cts_opt): Resizes buffers, balances clock loads, and resolves hold timing violations.
4. Global & Detailed Routing: Connects all signal nets using multi-layer metal tracks and vias.
5. Antenna Diode & Metal Fill Insertion: Protects gate oxides and balances planar metal density for CMP.
6. Parasitic RC Extraction (SPEF): Extracts wire parasitics into standard exchange format.
7. Signoff STA & Physical Verification: Closes timing slack and runs DRC/LVS before final GDSII export.