02Front-End

RTL Design & Functional Verification

The digital logic realization phase. Hardware designers translate the System Specification into synthesizable Register-Transfer Level (RTL) code using Verilog, SystemVerilog, or VHDL. Verification engineers build comprehensive UVM testbenches, assertions, and constrained-random simulations to mathematically and functionally prove 100% coverage before committing to physical logic gates.

⏱️4–12 weeksTypical Duration

👥RTL Designer + DV EngineerKey People

📄Lint/Sim-Clean RTL → Netlist ReadyDeliverable

🔧Simulators, Linters, SVATool Phase

SECTION 01 — STAGE DESCRIPTION

What Happens in RTL Design & Verification?

🧩 The RTL & Verification Engineer's Job

At Stage 02, the chip's logical architecture becomes concrete digital hardware description. The RTL designer describes how registers (flip-flops) capture state and how combinational Boolean logic transforms data on every rising clock edge. Every finite state machine (FSM), arithmetic logic unit (ALU), bus arbiter, and peripheral controller is implemented with strict synthesizability rules — avoiding combinational feedback loops, unintended latches, and clock glitches.

Simultaneously, the Design Verification (DV) engineer builds an isolated verification environment using SystemVerilog and UVM (Universal Verification Methodology). Constrained-random stimulus generators, functional coverage monitors, and SystemVerilog Assertions (SVA) test corner cases — such as buffer overflows, pipeline stalls, reset sequences, and bus protocol illegal states.

Static linting tools (SpyGlass, Verilator) verify code quality, ensuring naming conventions, complete sensitivity lists, and proper port matching. Only when the RTL achieves 100% statement, branch, toggle, and functional coverage is it signed off for synthesis.

🏗️

Analogy: Like writing the source code for an operating system and running millions of automated unit tests. A software bug can be patched over the air, but a hardware logic bug fabricated into silicon bricks the chip. Finding a logic bug in RTL simulation takes 10 minutes; finding it in silicon requires a $2M+ mask re-spin and 6 months of schedule slip.

📋 What System Spec Provides

System architecture document & block diagram
Instruction Set Architecture (ISA) & register map
Interface protocols (AXI, AHB, APB, Wishbone, SPI)
Clock domain definitions & target frequencies
Power domain partitions & sleep modes
Initial SDC timing constraints & PPA targets

📐 What the RTL/DV Team Produces

Synthesizable RTL source files (.v / .sv / .vhd)
SystemVerilog / UVM testbench suite & VIP models
SystemVerilog Assertions (SVA) monitor files
Lint signoff report (zero high-severity violations)
Code coverage report (100% line, branch, toggle)
Functional coverage matrix mapped to specifications

SECTION 02 — INPUT / OUTPUT FILES

Files Flow: Stage 02 Inputs & Outputs

📥 INPUTS

system_spec.pdf

Architectural specification — module definitions, memory addresses, interface tables, pipeline stages

From: Stage 01 System Spec

constraints.sdc

Clock frequency targets, setup/hold margins, IO pin delays for timing budget awareness

From: Stage 01 Architect

register_map.csv

Control/Status Register (CSR) definitions, bitfields, reset values, read/write access policies

From: Stage 01 System Spec

⚙️ STAGE 02 PROCESS

① RTL Coding & FSM Structuring

② Static Lint Checking

③ Testbench Architecture (UVM)

④ Constrained-Random Simulation

⑤ Assertion-Based Verification

⑥ Coverage Closure & Sign-off

↓

📤 OUTPUT FILES

picorv32_top.v

Lint-clean, synthesizable Verilog/SystemVerilog source tree covering all functional blocks

→ Used by: Stage 03 Logic Synthesis

testbench.sv

Self-checking SystemVerilog testbench suite with automated scoreboards & checkers

→ Used by: Regression Test Suites

waveforms.vcd / .fsdb

Value Change Dump / Fast Signal Database recording cycle-accurate internal net transitions

→ Used by: Power Analysis (VCD), Debug

📊 REPORTS / SIGNOFF

lint_summary.rpt

Static rule checking report proving 0 latches, 0 multi-driven nets, 0 unused width mismatches

Signoff: RTL Lead

coverage_signoff.rpt

Verification signoff report: 100% statement, branch, toggle, state, and functional cross-coverage

Signoff: DV Lead

SECTION 03 — REAL PROJECT WALKTHROUGH

PicoRV32 on SKY130: From HDL to Verified RTL

🔬 OPEN-SOURCE PROJECT

ProjectPicoRV32 — Minimal RISC-V RV32IMC Processor

Sourcegithub.com/YosysHQ/picorv32

PDKSkyWater SKY130 (sky130_fd_sc_hd) — 130nm open PDK

Target50 MHz, 300µm × 300µm die, < 5 mW active

STEP 1

Synthesizable Verilog RTL Core (picorv32.v snippet)

// picorv32.v - RISC-V 32-bit Core Execution Unit
module picorv32_alu (
    input  wire [31:0] a,
    input  wire [31:0] b,
    input  wire [ 3:0] alu_op,
    output reg  [31:0] alu_out,
    output wire        alu_zero
);
    always @(*) begin
        case (alu_op)
            4'b0000: alu_out = a + b;           // ADD
            4'b0001: alu_out = a - b;           // SUB
            4'b0010: alu_out = a & b;           // AND
            4'b0011: alu_out = a | b;           // OR
            4'b0100: alu_out = a ^ b;           // XOR
            4'b0101: alu_out = a << b[4:0];     // SLL (Shift Left Logical)
            4'b0110: alu_out = a >> b[4:0];     // SRL (Shift Right Logical)
            4'b0111: alu_out = $signed(a) >>> b[4:0]; // SRA (Arithmetic)
            4'b1000: alu_out = ($signed(a) < $signed(b)) ? 32'd1 : 32'd0; // SLT
            4'b1001: alu_out = (a < b) ? 32'd1 : 32'd0;                   // SLTU
            default: alu_out = 32'h0000_0000;
        endcase
    end
    assign alu_zero = (alu_out == 32'h0000_0000);
endmodule

STEP 2

Testbench Simulation & Assertion Verification Command

# Run cycle-accurate simulation with Icarus Verilog & generate VCD
iverilog -g2012 -o picorv32_sim picorv32_tb.v picorv32.v
vvp picorv32_sim +firmware=firmware.hex +vcd

# Alternatively, run high-speed multi-threaded simulation with Verilator
verilator --cc --exe --build -Wall --trace \
    -Wno-UNUSED -Wno-DECLFILENAME \
    picorv32.v picorv32_tb.cpp

# Execute compiled C++ simulator binary
./obj_dir/Vpicorv32

STEP 3

Functional Verification & Coverage Output (picorv32_tb.log)

=== PicoRV32 Verification Testsuite Signoff ===
[TB] Initializing memory from firmware.hex (2048 words)...
[TB] CPU Reset deasserted at t = 40 ns (sys_clk = 50 MHz)
[TB] Testcase 01: RV32I Base ALU Instructions ....... PASS (142 cycles)
[TB] Testcase 02: RV32M Hardware Multiply/Divide .... PASS (280 cycles)
[TB] Testcase 03: RV32C Compressed Instructions ..... PASS (94 cycles)
[TB] Testcase 04: Memory-Mapped UART & GPIO ......... PASS (520 cycles)
[TB] Testcase 05: Timer Interrupt & Trap Handler .... PASS (310 cycles)
-----------------------------------------------------------------
[SVA] Formal Property Checks: 48 / 48 Passed (0 Violations)
[COV] Statement Coverage   : 100.0% (1,842 / 1,842 lines)
[COV] Branch Coverage      : 99.4%  (498 / 501 branches)
[COV] Functional Coverage  : 100.0% (All ISA opcodes exercised)
STATUS: STAGE 02 RTL VERIFICATION COMPLETE - PASS

SECTION 04 — EDA TOOLS

Tools Used in RTL Design & Verification Stage

Industry workflows rely on powerful commercial digital simulators and formal property checkers to guarantee cycle-accurate correctness, while modern open-source toolchains provide fast, scriptable verification for rapid iteration.

Task	🏭 Synopsys	🔷 Cadence	🟧 Siemens EDA	🔓 Open-Source
HDL Logic Simulation (Verilog/SV/VHDL)	Synopsys VCS	Cadence Xcelium	Siemens QuestaSim / ModelSim	Icarus Verilog · Verilator · GHDL
RTL Static Linting & Coding Style Checks	Synopsys SpyGlass Lint	Cadence JasperGold Superlint	Siemens Questa Lint	Verilator (--lint-only) · svlint
Assertion-Based & Formal Property Proofs	Synopsys VC Formal	Cadence JasperGold Formal	Siemens Questa Formal	SymbiYosys (sby) · Z3 · Boolector
Code & Functional Coverage Analytics	Synopsys Unified Coverage (URG)	Cadence IMC (Incisive Metrics)	Siemens Questa Coverage	Covered · Verilator Coverage
Waveform Viewing & Signal Debugging	Synopsys Verdi	Cadence SimVision	Siemens Questa Visualizer	GTKWave · Surfer