Automated Physical Design Execution Flow
Walk through each discrete phase of modern semiconductor physical synthesis: from high-level Verilog RTL synthesis with Yosys down to detailed DRC-clean routing with TritonRoute.
01. System Spec & Customer Handover Protocol
Before physical logic synthesis, inspect what customer input files (.sdc, .upf, .lef, .lib, .pdf), constraints, and PDK deliverables are shared with designers, featuring the IoT-Sense-RV32 SoC benchmark case study & battery calculator.
RTL-to-GDSII Automated EDA Pipeline
Explore every physical design stage from HDL synthesis to signoff GDSII layout. Click on any stage below to inspect inputs, outputs, commands, and QoR statistics.
RTL Synthesis
YosysTranslates high-level Verilog/SystemVerilog RTL into a technology-mapped gate-level netlist using standard cell target libraries (.lib).
- design.v
- sky130_fd_sc_hd.lib
- constraints.sdc
- synthesis.v
- synthesis.stat.json
Floorplan & PDN Grid
OpenROAD FPEstablishes die core aspect ratio, places SRAM macro blocks, defines IO pins, and generates the Power Distribution Network (PDN) metal mesh.
- synthesis.v
- sky130.lef
- tech.lef
- floorplan.def
- pdn.def
Global & Detailed Placement
RePlAce / OpenROADPerforms electrostatics-based analytical global placement followed by legalizer and detailed placement to minimize wirelength & congestion.
- floorplan.def
- sky130_fd_sc_hd.lef
- placed.def
- congestion_heatmap.png
Clock Tree Synthesis (CTS)
TritonCTSConstructs balanced clock tree distribution network using buffer insertion to minimize clock latency, skew, and hold time violations.
- placed.def
- clock_tree.sdc
- clk_buffers.lib
- cts.def
- cts_skew.rpt
Global & Detailed Routing
FastRoute / TritonRouteGenerates detailed track assignment across metal layers (Met1 to Met5) while enforcing strict design rule checking (DRC) & antenna rules.
- cts.def
- routing_guides.guide
- routed.def
- spef_parasitics.spef
Signoff STA & GDSII Streaming
OpenSTA & KLayoutExecutes multi-corner Static Timing Analysis (STA), crosstalk parasitic delay calculation, and streams out final GDSII/OASIS layout format.
- routed.def
- spef_parasitics.spef
- sky130.lib
- chip_final.gds
- sta_wns_tns.rpt